coreboot-announce

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23 discussions

SerialICE - Qemu based x86 firmware debugger
by Stefan Reinauer 06 Jun '09

06 Jun '09

Dear x86 hardware and low-level software developers and enthusiasts! coresystems GmbH is proud to release the first version of our "Integrated Circuit Emulator over Serial", short SerialICE. This piece of software consists of two parts: - a serial console "rom shell" compiled with romcc, with minimal footprint. (Due to romcc the image is still 128k because it did not fit in 64k but this can be optimized later) - a patch to Qemu 0.10.4, which adds a new "SerialICE" machine. Short description: SerialICE is a BIOS/Firmware debugging tool. It allows you to run and observe BIOS images (such as coreboot®: http://www.coreboot.org/) written for real hardware in Qemu (http://www.nongnu.org/qemu) for debugging purposes. Thanks to Qemu's compelling feature set, it's also possible to debug this BIOS code with GNU GDB. SerialICE can be downloaded from http://www.coresystems.de/download/SerialICE-1.0.tar.bz2 With "qemu -m serialice -serialice /dev/ttyS0 -L path-to-your-bios.bin-dir -hda /dev/zero" you can run an arbitrary BIOS binary written for your target hardware in Qemu, thus logging all IO and memory accesses. Those operations will additionally be transmitted to the target system's shell and are executed there, while their results are submitted back to Qemu. Operations sent to the target: - memory reads/writes (some of them) - IO reads/writes - MSR reads/writes - CPUID calls (the bios code path might rely on this) Note: The code is very experimental and still buggy, but it was already useful in some debugging scenarios we had and was able to reveil information that would normally only be available with a hardware debugger of the price of a new car. Don't expect SerialICE to completely replace a ICE/JTAG/ITP device, but it might just work for your case, as it did for us. The code needs minimal board/chipset specific setup in order to have serial console operational for communication with Qemu. See mainboard/* for an example. This release contains demo code for two mainboards with Intel® CPUs. Also, some hardware accesses have to be caught in the Qemu code (hw/serialice.c) in order to prevent the system from locking up (ie. by disabling the serial console). Known issues: - The code is ugly, and the Qemu part is light years from a state where integration would be possible. - infrastructure for compiling with gcc + xmmstack is there, but it still fails with some odd assembler errors. This should push the SerialICE rom shell clearly below 64k again. - microcode updates from within emulated ROM code will fail. - some rarely used calls of cpuid will not give the correct information (those using two registers for input) Special thanks go to * Alex Graf for listening to my odd ideas while embedded world and supporting this project from early on. * Paul Brook for helping me find the last bug that prevented surviving all of RAM initialization on one board. * Patrick Georgi for Development and Testing. * Ron Minnich for advice and encouragement. * Eric Biederman for romcc Comments and patches are of course very welcome! Best regards, Stefan Reinauer -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

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flashrom 0.9.0 has been released!
by Carl-Daniel Hailfinger 04 May '09

04 May '09

The flashrom developers are happy to announce the release of flashrom 0.9.0. flashrom is a utility for reading, writing, erasing and verifying flash ROM chips. flashrom is often used to flash BIOS/coreboot/firmware images because it allows you to update your BIOS/coreboot/firmware without opening the computer and without any special boot procedures. After nine years of development and constant improvement, we have added support for every BIOS flash ROM technology present on x86 mainboards and every flash ROM chip we ever saw in the wild. Highlights of flashrom include: - Parallel, LPC, FWH and SPI flash interfaces. - 157 flash chip families and half a dozen variants of each family. - Flash chip package agnostic. DIP32, PLCC32, DIP8, SO8/SOIC8, TSOP32, TSOP40 and more have all been verified to work. - 75 different chipsets, some with multiple flash controllers. - Special mainboard enabling code for dozens of nonstandard mainboards. - No physical access needed. root access is sufficient. - No bootable floppy disk, bootable CD-ROM or other media needed. - No keyboard or monitor needed. Simply reflash remotely via SSH. - No instant reboot needed. Reflash your ROM in a running system, verify it, be happy. The new firmware will be present next time you boot. - Crossflashing and hotflashing is possible as long as the flash chips are electrically and logically compatible (same protocol). Great for recovery. - Scriptability. Reflash a whole pool of identical machines at the same time from the command line. It is recommended to check flashrom output and error codes. - Speed. flashrom is much faster than vendor flash tools. - Supports Linux, FreeBSD, DragonFly BSD, Solaris, Mac OS X. Please refer to the README for build instructions. Thanks go to everyone who contributed to flashrom over the years and especially to Li-Ta Lo for starting this project. Please note that rewriting your flash chip can be dangerous and flashrom developers make no guarantees whatsoever. That said, many users have successfully replaced proprietary tools such as awdflash, amiflash and afudos with flashrom. flashrom has its own home page at http://coreboot.org/flashrom flashrom 0.9.0 can be downloaded in various ways: Anonymous checkout from the subversion repository at svn://coreboot.org/flashrom/tags/flashrom-0.9.0 Tarball download at http://qa.coreboot.org/releases/flashrom-0.9.0.tar.gz http://qa.coreboot.org/releases/flashrom-0.9.0.tar.bz2 with GPG signatures at http://qa.coreboot.org/releases/flashrom-0.9.0.tar.{gz,bz2}.asc

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Welcome to the coreboot announcement mailing list!
by Stefan Reinauer 15 Jan '09

15 Jan '09

Hi, welcome to the coreboot announcement mailing list. This list will get news and updates on coreboot for all those that do not find the time to follow the daily busy discussion, coding and details! Feedback is welcome! Best regards, Stefan Reinauer -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

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