[SerialICE] New patch to review for serialice: e9102c9 VX900: Fix decoding of southbridge MMIO BAR

[Alexandru Gagniuc (mr.nuke.me@gmail.com)]

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3799

-gerrit

commit e9102c9a51691b3727d88a8b47b0566523718cb7
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Mon Jul 22 16:00:34 2013 -0500

    VX900: Fix decoding of southbridge MMIO BAR
    
    Change-Id: I94ef658fb90e0c36a038e4f87a0b25e444af7e40
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
 SerialICE/simba/chipset/via_bars.lua | 13 ++++++++-----
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/SerialICE/simba/chipset/via_bars.lua b/SerialICE/simba/chipset/via_bars.lua
index 1dca148..838aba2 100644
--- a/SerialICE/simba/chipset/via_bars.lua
+++ b/SerialICE/simba/chipset/via_bars.lua
@@ -1,15 +1,18 @@
 
-function sb_pcie_bar(dev, reg, base)
-	local baseaddr = bit32.lshift(base, 16)
-	local size = 64*1024
+function sb_mmio_bar(f, action)
+	-- This MMIO space is used for SPI and CEC control
+	f.dev.mmio.name = "SB_MMIO"
+	f.dev.mmio.val = bit32.lshift(bit32.band(action.data, 0xfff0), 8)
+	f.dev.mmio.size = 0x10000
 
-	pcie_mm_cfg_bar(baseaddr, size)
+	generic_mmio_bar(f.dev.mmio)
 end
 
 dev_sb = {
 	pci_dev = pci_bdf(0,0x11,0,0),
 	name = "sb",
 	bar = {},
+	mmio = { f = nil },
 }
 
 function nb_pcie_bar(dev, reg, base)
@@ -25,7 +28,7 @@ dev_nb = {
 }
 
 function northbridge_vx900()
-	pci_cfg16_hook(dev_sb, 0xbd, "SB_PCI", sb_pcie_bar)
+	pci_cfg32_hook(dev_sb, 0xbc, "SB_MMIO", sb_mmio_bar)
 	pci_cfg32_hook(dev_nb, 0x0, "NB_PCI", nb_pcie_bar)
 end