[SerialICE] New patch to review for serialice: f91e38b Make PCIe handling a bit more generic

[Patrick Georgi (patrick@georgi-clan.de)]

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/463

-gerrit

commit f91e38b253917c3dc505ea8dc2f8f8f4029fdd03
Author: Patrick Georgi <patrick.georgi at secunet.com>
Date:   Thu Dec 1 13:43:36 2011 +0100

    Make PCIe handling a bit more generic
    
    Change-Id: I1099969ed14debfd30f00f5efd10a9a6f3198d22
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
---
 SerialICE/scripts/serialice.lua |   41 ++++++++++++++++++++++++++++++--------
 1 files changed, 32 insertions(+), 9 deletions(-)

diff --git a/SerialICE/scripts/serialice.lua b/SerialICE/scripts/serialice.lua
index 535cb0b..a41988a 100644
--- a/SerialICE/scripts/serialice.lua
+++ b/SerialICE/scripts/serialice.lua
@@ -50,6 +50,10 @@ function size_data(size, data)
 	end
 end
 
+function pci_bdf(bus, dev, func, reg)
+	return 0x80000000 + bus*65536 + dev*2048 + func*256 + reg
+end
+
 function new_list()
 	return { list = nil }
 end
@@ -72,6 +76,7 @@ function walk_list(list, ...)
 	return false
 end
 
+io_write_hooks = new_list()
 msr_write_hooks = new_list()
 msr_read_hooks = new_list()
 
@@ -102,6 +107,27 @@ function(addr, hi, lo, filtered)
 	return false
 end)
 
+function trim (s)
+	return (string.gsub(s, "^%s*(.-)%s*$", "%1"))
+end
+
+mainboard = trim(SerialICE_mainboard)
+
+if northbridge == "intel-i945" then
+	prepend_to_list(io_write_hooks, function(port, size, data, filter)
+		if port == 0xcfc then
+			-- Catch PCIe base address
+			if SerialICE_pci_device == pci_bdf(0,0,0,0x48) then
+				PCIe_bar  = bit.band(0xfc000000,data) % 0x100000000
+				PCIe_size = 64 * 1024 -- hard coded for now.
+				printf("PCIe BAR set up: 0x%08x\n", PCIe_bar)
+				return true
+			end
+		end
+		return false
+	end)
+end
+
 -- In the beginning, during RAM initialization, it is essential that 
 -- all DRAM accesses are handled by the target, or RAM will not work
 -- correctly. After RAM initialization, RAM access has no "special"
@@ -187,6 +213,10 @@ PCIe_size = 0
 --   data	Value returned if the write was *not* intercepted
 
 function SerialICE_io_write_filter(port, size, data)
+	filter = { filter = false, data = data }
+	if walk_list(io_write_hooks, port, size, data, filter) then
+		return filter.filter, filter.data
+	end
 	-- **********************************************************
 	--
 	-- PCI config space handling
@@ -205,13 +235,6 @@ function SerialICE_io_write_filter(port, size, data)
 			return true, data
 		end
 
-		-- Catch PCIe base address
-		if SerialICE_pci_device == 0x80000048 then
-			PCIe_bar  = bit.band(0xfc000000,data)
-			PCIe_size = 64 * 1024 -- hard coded for now.
-			printf("PCIe BAR set up: 0x%08x\n", PCIe_bar)
-		end
-
 		return false, data
 	end
 
@@ -369,7 +392,7 @@ function SerialICE_memory_read_filter(addr, size)
 	if	addr >= 0xfff00000 and addr <= 0xffffffff then
 		-- ROM accesses go to Qemu only
 		return false, true, 0
-	elseif	addr >= 0xf0000000 and addr <= 0xf3ffffff then
+	elseif	addr >= PCIe_bar and addr <= (PCIe_bar + PCIe_size) then
 		-- PCIe MMIO config space accesses are
 		-- exclusively handled by the SerialICE
 		-- target
@@ -448,7 +471,7 @@ function SerialICE_memory_write_filter(addr, size, data)
 		printf("\nWARNING: write access to ROM?\n")
 		-- ROM accesses go to Qemu only
 		return false, true, data
-	elseif	addr >= 0xf0000000 and addr <= 0xf3ffffff then
+	elseif	addr >= PCIe_bar and addr <= (PCIe_bar + PCIe_size) then
 		-- PCIe MMIO config space accesses are
 		-- exclusively handled by the SerialICE
 		-- target