[SeaBIOS] [PATCH v3] fw/msr_feature_control: add support to set MSR_IA32_FEATURE_CONTROL

[Laszlo Ersek]

On 07/06/16 08:28, Haozhong Zhang wrote:
> Hi Ashok,
> 
> On 07/06/16 02:18, Paolo Bonzini wrote:
>>> I forgot to restore MSR_IA32_FEATURE_CONTROL in the resume path, and
>>> MSR_IA32_FEATURE_CONTROL is zero after S3 resume.
>>
>> This is a bug.  Sorry Laszlo. :)
>>
>>> Not restore MSR_IA32_FEATURE_CONTROL during S3 resume does not affect
>>> at least Linux guest (tested 4.5). Current QEMU may advise the guest
>>> firmware to set bit 20 (for LMCE), bit 2 (for VMX) and bit 0 (lock
>>> bit).
>>> - For LMCE, Linux only checks bit 20 and bit 0 at boot time and then
>>>   keeps using the result even after resume.
>>
>> On real hardware, LMCE would not be enabled after resume.  I'm not
>> sure what would happen, but it wouldn't be good.
> 
> Could you help to check if the LMCE bit in MSR_IA32_FEATURE_CONTROL is
> set after S3 resume on the real hardware?

The SDM says that IA32_FEATURE_CONTROL is zeroed on logical processor reset.

  23.7 ENABLING AND ENTERING VMX OPERATION

  [...] VMXON is also controlled by the IA32_FEATURE_CONTROL MSR (MSR
  address 3AH). This MSR is cleared to zero when a logical processor is
  reset. [...]

Thanks
Laszlo