[SeaBIOS] Does SeaBIOS support eMMC?

[Scheithauer, Mario]

> -----Ursprüngliche Nachricht-----
> Von: Kevin O'Connor [mailto:kevin at koconnor.net]
> Gesendet: Dienstag, 12. Januar 2016 18:26
> An: Scheithauer, Mario
> Cc: seabios at seabios.org
> Betreff: Re: [SeaBIOS] Does SeaBIOS support eMMC?
> 
> On Tue, Jan 12, 2016 at 05:07:08PM +0000, Scheithauer, Mario wrote:
> > > -----Ursprüngliche Nachricht-----
> > > Von: Kevin O'Connor [mailto:kevin at koconnor.net]
> > > Gesendet: Dienstag, 12. Januar 2016 17:15
> > > An: Scheithauer, Mario
> > > Cc: seabios at seabios.org
> > > Betreff: Re: [SeaBIOS] Does SeaBIOS support eMMC?
> > >
> > > On Mon, Jan 11, 2016 at 03:49:19PM +0000, Scheithauer, Mario wrote:
> > > > First I will clone a new coreboot with an actual SeaBIOS. After
> > > > that I will give you a new log.
> > > > But second I think sdcard setup is not ready for JEDEC Standard
> > > > 84-B51. Maybe I'm wrong with that.
> > >
> > > I did use that JEDEC standard as a reference when writing the code.
> > >
> > > > Our eMMC flash has a size of 8GB but recognized are only 2GB and I
> > > > believe for switching to high-speed mode there are some more steps
> > > > necessary.
> > >
> > > SeaBIOS does not attempt to enable high speed mode or to enable
> > > multiple read data lines.  The goal is just to boot the OS - the OS
> > > can then enable whatever optimizations it wants.
> >
> > Well, I understand.
> >
> > > The drive is showing up as an 2TB drive, so something is clearly
> > > wrong with the size detection.  Upon attempting to boot from the drive, a read
> CRC error occurs.
> > > I wonder if the drive is not in sync with the controller on the
> > > number of data lines in use.
> >
> > I believe the mechanism to determine the size for eMMC4.5 devices are
> differently than up to now.
> > However, that is no problem.
> 
> Yes - on v4.0 and later MMC devices SeaBIOS reads from the size from the
> EXT_CSD register.  The log indicates that SEND_EXT_CSD was sent, so SeaBIOS
> is recognizing the hardware version, and the command completes without error.
> But the size results do look suspect.
> 
> I double checked, and other users are reporting success on SeaBIOS with v4+
> eMMC devices.
> 
> > > How many SD/MMC devices are in this machine?  In addition to the
> > > eMMC drive that is detected, another device starts the detection on
> > > a different controller but fails earlier in the process.  Is that expected?
> >
> > We have two Storage Control Cluster, one for SDIO / SD and one for eMMC 4.5.
> > In my opinion a device should be only at the second SCC connected.
> > However, should the last version of Lubuntu not work with that?
> > Lubuntu detects an mmc block device (mmcblk0boot0 and mmcblk0boot1).
> > But the size is not correct. Both blocks have a size of 256kB.
> > Fdisk cannot install a partition and ends with the error message 'failed to write
> disklabel: Operation not permitted'.
> > Maybe we have a hardware issue, because the eMMC device is directly on the
> board.
> 
> To verify if Linux can use the device, I suggest disabling CONFIG_SDCARD in
> SeaBIOS, hard poweroff the machine for a minute (and pull the battery if it is a
> laptop), and then boot Linux from another media.  Linux should be able to
> detect/read/write the device.  We've seen that some eMMC devices can get stuck
> in a bad mode, so a full power off may be needed.

I had already tried out this and the behavior of Linux with and without CONFIG_SDCARD in SeaBIOS is the same.
It has no influence on it.

> If Linux can't detect/read/write the device, then I suggest addressing that before
> looking at the SeaBIOS code.
> 
> Otherwise, can you try the SeaBIOS patch below and report the additional
> debugging?
> 
> -Kevin
> 
> 
> --- a/src/hw/sdcard.c
> +++ b/src/hw/sdcard.c
> @@ -490,6 +490,8 @@ sdcard_controller_setup(struct sdhci_s *regs, int prio)
>              , readw(&regs->controller_version)
>              , readl(&regs->cap_lo), readl(&regs->cap_hi));
>      sdcard_reset(regs, SRF_ALL);
> +    dprintf(1, "hc1=%x hc2=%x\n"
> +            , readb(&regs->host_control), readw(&regs->host_control2));
>      writew(&regs->irq_signal, 0);
>      writew(&regs->irq_enable, 0x01ff);
>      writew(&regs->irq_status, readw(&regs->irq_status)); @@ -515,6 +517,8 @@
> sdcard_controller_setup(struct sdhci_s *regs, int prio)
>          free(drive);
>          goto fail;
>      }
> +    dprintf(1, "later hc1=%x hc2=%x\n"
> +            , readb(&regs->host_control), readw(&regs->host_control2));
>      return;
>  fail:
>      writeb(&regs->power_control, 0);

Host Control Register (HOST_CTL offset 28h) is at the beginning of the function 'sdcard_controller_setup' 0x00 as well as at the end.
The same I can see at the Host control2 Register - 0x0000 for the 1st printf and 0x0000 for the second printf.

Thanks,
Mario