[SeaBIOS] INT 1A - PCI Services supported?

[Bob Moore]

Sorry for the bother people.  I now see that PCI Services is supported (and configured in my source tree).  I am now executing code in the 16 bit handler.

Thanks.

Bob

From: Bob Moore
Sent: Tuesday, February 16, 2016 4:50 PM
To: 'seabios at seabios.org'
Subject: INT 1A - PCI Services supported?

Hello again,

I have a need in my option ROM to interrogate devices identified by the BIOS PCI bus enumeration process.  It seems like the most straight forward way to do this would be to use INT 1A assuming seaBios supports PCI 2.0 or later, to search for all instances of devices which I'm interested in.  Can anyone confirm whether seaBios supports PCI 2.0 or later?  I see a hardcoded org at 0xfe6e in romlayout.S that appears to be the entry to that handler.  I've tried using the INT instruction as well as calling directly to 0xf000fe6e.  Direct calls result in KVM crash as below.  I suspect this is due to not using the proper 16/32 bit call interface.  Using INT 1A I don't appear to be going through this code at all.

Thanks.

Bob

Running option rom at ca80:0003
KVM internal error. Suberror: 1
emulation failure
EAX=0000b102 EBX=0000ffff ECX=00008547 EDX=000011f8
ESI=00000000 EDI=000058b0 EBP=00000000 ESP=00006e4c
EIP=f000fe6e EFL=00010202 [-------] CPL=0 II=0 A20=1 SMM=0 HLT=0
ES =f000 000f0000 ffffffff 00809300
CS =ca80 000ca800 ffffffff 00809b00
SS =0000 00000000 ffffffff 00809300
DS =0000 00000000 ffffffff 00809300
FS =0000 00000000 ffffffff 00809300
GS =0000 00000000 ffffffff 00809300
LDT=0000 00000000 0000ffff 00008200
TR =0000 00000000 0000ffff 00008b00
GDT=     000f59c0 00000037
IDT=     00000000 000003ff
CR0=00000010 CR2=00000000 CR3=00000000 CR4=00000000
DR0=0000000000000000 DR1=0000000000000000 DR2=0000000000000000 DR3=0000000000000000
DR6=00000000ffff0ff0 DR7=0000000000000400
EFER=0000000000000000
Code=00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 <00> 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
qemu: terminating on signal 2

Robert (Bob) L Moore
Firmware Engineer
CIBU Platform
o: 719-799-4642 (ext. 244642)
robert.moore at hgst.com<mailto:robert.moore at hgst.com>

[cid:image001.png at 01D13689.346E0520]
1975 Research Pkwy, Suite 135
Colorado Springs, CO 80920
www.wdc.com<http://www.wdc.com/>

Western Digital Corporation (and its subsidiaries) E-mail Confidentiality Notice & Disclaimer:

This e-mail and any files transmitted with it may contain confidential or legally privileged information of WDC and/or its affiliates, and are intended solely for the use of the individual or entity to which they are addressed. If you are not the intended recipient, any disclosure, copying, distribution or any action taken or omitted to be taken in reliance on it, is prohibited. If you have received this e-mail in error, please notify the sender immediately and delete the e-mail in its entirety from your system.
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.seabios.org/pipermail/seabios/attachments/20160217/96b04c75/attachment.html>
-------------- next part --------------
A non-text attachment was scrubbed...
Name: image001.png
Type: image/png
Size: 6257 bytes
Desc: image001.png
URL: <http://www.seabios.org/pipermail/seabios/attachments/20160217/96b04c75/attachment.png>