[SeaBIOS] [PATCH] searialio: Support for mmap serial ports
Ricardo Ribalda Delgado
ricardo.ribalda at gmail.com
Tue Dec 20 18:48:08 CET 2016
Thanks for your fast response :)
On Tue, Dec 20, 2016 at 5:48 PM, Kevin O'Connor <kevin at koconnor.net> wrote:
> Does this chipset hardcode the uart at that memory address or is that
> address part of a PCI BAR? If it's on a PCI device it would be
> preferable to do a pci scan and find the address.
Seems that it is hardcoded. Check out
There are two UART controllers in Kern.
The UART registers are memory-mapped. UART
controller 0 registers range from FEDC_6000h
to FEDC_6FFFh. UART controller 1 registers
range from FEDC_8000h to FEDC_8FFFh.
>> - outb(c, CONFIG_DEBUG_SERIAL_PORT+SEROFF_DATA);
>> + serial_outb(c, CONFIG_DEBUG_SERIAL_PORT, SEROFF_DATA);
> The above code (along with serial_debug_flush() ) can be called in
> 16bit mode and writing to a 32bit memory address there can cause
> failures (crashes or memory corruption). Simplest solution is
> probably to only write to memory if !MODE_SEGMENT - thus providing
> debug support only in 32bit mode (init and boot phases).
Will fix and resend. Thanks!
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