[SeaBIOS] IDT issue

[Naresh G. Solanki]

Hi All,

I was facing difficulty in enabling 0xE0000 & 0xF0000 segment on intel atom
e6xx processor.

As per guide (atom e6xx minimum boot requirements) in table 15 it was
mentioned that the segment can be enabled by setting bit 1 & 2 of port 0
reg offset 3. I tried but it failed.

I needed it to execute seabios successfully.

By trial & error I found that instead of port 0 if I tried setting the bits
in port 2 offset 3 , it served my purpose completely.( I think its wrongly
documented in the guide I was refering)

Now I'm able to execute seabios.

- N Solanki
On Thu, Mar 19, 2015 at 07:24:09PM +0530, Naresh G. Solanki wrote:
> As per the document
>
>
http://www.intel.com/content/www/us/en/intelligent-systems/queens-bay/atom-e6xx-boot-requirements-app-note.html
>
> Table 15 specifies about how to enable 0xE0000/0xF0000 segment.
> As per that I have enabled the segment. Is that OK.

That sounds like it.  But, if it still doesn't work, then it is
something else.  :-)

You could also try asking on the coreboot list.  They are likely more
familiar with the intel chipsets.

-Kevin
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