[SeaBIOS] [Qemu-devel] [PATCH v4 2/3] target-i386: reserve RCRB mmio space in ACPI DSDT table

Paulo Alcantara pcacjr at zytor.com
Mon Jun 22 14:53:23 CEST 2015

On Mon, June 22, 2015 5:40 am, Michael S. Tsirkin wrote:
> On Sun, Jun 21, 2015 at 09:37:02PM -0300, Paulo Alcantara wrote:
>> This block is mapped into memory space, using the Root Complex Base
>> Address (RCBA) register of the PCI-to-LPC bridge. Accesses in this space
>> must be limited to 32-(DW) bit quantities. Burst accesses are not
>> allowed.
>> All Chipset Configuration Registers are located in this 16KiB space.
>> Signed-off-by: Paulo Alcantara <pcacjr at zytor.com>
> Just to make sure, the device is in fact only functional
> if it's enabled using the property, correct?
> In that case please add it conditionally to the SSDT instead.

No need to add it conditionally in SSDT. In fact, what this patch does is
just reserving the MMIO region but the firmware and OS is free to set RCBA
to whatever address it wants. For instance, the OVMF is currently setting
RCBA to that address already so, if running on pc-q35-2.3 (or older), the
TCO will not work either since it was not initialised (enable_tco ==

In order to test Linux's iTCO_wdt kernel module I had to patch SeaBIOS
(patch still pending, BTW) and OVMF to set RCBA BAR -- neither affected by
this DSDT's change -- because the module requires RCRB to access
GCS_NO_REBOOT bit flag to decide whether or not reboot the system on
second TCO timeout. Otherwise the module won't be loaded up and no
"/dev/watchdog" interface.



Paulo Alcantara, C.E.S.A.R
Speaking for myself only.

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