[SeaBIOS] [Qemu-devel] [PATCH V2] pci: fixes to allow booting from extra root pci buses.

Marcel Apfelbaum marcel at redhat.com
Mon Jun 15 11:02:23 CEST 2015

On 06/15/2015 09:50 AM, Gerd Hoffmann wrote:
>    Hi,
>> I'm wondering whenever things become easier if we add config registers
>> to the pxb, where the firmware can program the bus number range and we
>> can use the config register base as a way to specify which pxb we are
>> referring to ?
> ... and, while thinking about ben's reply elsewhere in this thread,
> maybe even decouple the whole thing from the primary root bus?  You
> can't program the devices via 0x0cf8 then, but we could add a mmconfig
> bar to the host bridge device ...

Hi Gerd,

I thought about it of course, but it seemed to me to be over-kill and
no real reason to do it. I would hove done it if:
- there would be a "generic" spec for such a host-bridge specifying
   at least the registers for the bus number. I didn't find anything =>
   => Seabios should be aware of a special QEMU device and look for it... ugly
- I would have seen how Seabios/coreboot program the above bus number.
   Again, didn't find the host-bridge programming code.
At last, I followed a 'real' PXB device, some old Intel snooping host bridge.

As always, I am open to ideas, but, the latest patches from Laszlo follows
Seabios way, and if OVMF can also handle it maybe we can stop:
"The use of logical bus number instead of bus index" discussion and
start arguing on something else. :)

I just want to say thank you to everybody involved,
a lot of information and good guidelines surfaced during this talk.

Until the next patch...

> cheers,
>    Gerd

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