[SeaBIOS] [PATCH] pci: enable SERR# for error forwording in bridge control register

Chen Fan chen.fan.fnst at cn.fujitsu.com
Thu Jan 29 02:21:53 CET 2015


Hi Paul,

Thanks for your attention and help me to correct the misspelling.

On 01/29/2015 06:21 AM, Paul Menzel wrote:
> Dear Chen,
>
>
> thank you for your patch.
>
> You misspelled `forw*a*rding` in the summary and the comment. I have
> some more nitpicks.
>
>
> Am Mittwoch, den 28.01.2015, 16:05 +0800 schrieb Chen Fan:
>> For PCIe device support AER(Advanced Error Reporting), from the
> Please add a space before `(`.
>
>> pcie spec 3.0 chapter 6.2.5, ERR_COR, ERR_NONFATAL, and ERR_FATAL
>> can be forwarded from the secondary interface to the primary interface,
>> only require the SERR# Enable bit in the Bridge Control register is set.
> … to be set.
>
>> and at the kernel side, we found only _HPP() method can enable
> *A*nd …
>
>> SERR#, So here we want to turn on this bit.
> s/So/so/
>
>> Signed-off-by: Chen Fan <chen.fan.fnst at cn.fujitsu.com>
> How did you test this?

I used qemu to test this patch, and also I had sent qemu
patchset series to improve aer report. if you have interest
in the patches, pls see:
http://lists.nongnu.org/archive/html/qemu-devel/2015-01/msg03947.html

>
>> ---
>>   src/fw/pciinit.c | 4 ++++
>>   1 file changed, 4 insertions(+)
>>
>> diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c
>> index 34279a4..28ed1af 100644
>> --- a/src/fw/pciinit.c
>> +++ b/src/fw/pciinit.c
>> @@ -310,6 +310,10 @@ static void pci_bios_init_device(struct pci_device *pci)
>>       /* enable memory mappings */
>>       pci_config_maskw(bdf, PCI_COMMAND, 0,
>>                        PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_SERR);
>> +    /* enable SERR# for forwording */
> forw*a*rding
>
>> +    if (pci->header_type & PCI_HEADER_TYPE_BRIDGE)
>> +        pci_config_maskw(bdf, PCI_BRIDGE_CONTROL, 0,
>> +                         PCI_BRIDGE_CTL_SERR);
>>   }
>>   
>>   static void pci_bios_init_devices(void)
> Otherwise this looks good.

Thanks,
Chen

>
>
> Thanks,
>
> Paul




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