[SeaBIOS] [Qemu-devel] [PATCH RFC V2 14/17] hw/pci: piix - suport multiple host bridges
marcel at redhat.com
Mon Feb 16 14:29:42 CET 2015
On 02/16/2015 03:00 PM, Alexander Graf wrote:
> On 16.02.15 10:54, Marcel Apfelbaum wrote:
>> From: Marcel Apfelbaum <marcel.a at redhat.com>
>> Instead of assuming it has only one bus, it
>> enumerates all the host bridges until it finds
>> the one with bus number corresponding with the
>> config register.
>> Signed-off-by: Marcel Apfelbaum <marcel at redhat.com>
Thank you for the review.
> How 440 specific is this? Wouldn't we need similar code for q35 and gpxe?
For gpxe: I have no idea.
For Q35: PCI Express have native support for extra root bridges by
having multiple Root Complexes(RC), but in this case each RC
handles its separate configuration space.
It may be possible to use the same hack as in PC to expose a
PCIe Root Port as a different host bridge and a primary bus behind
it, but it is out of this series scope.
The series aims to address the limitation that PC machines support
NUMA nodes for CPU/memory but not PCI.
Anyway, we can move the code when neeeded, but since it will
take some and the implementation is not certain, for the moment
is 440 specific.
More information about the SeaBIOS