[SeaBIOS] [Qemu-devel] [PATCH RFC V2 05/17] hw/acpi: remove from root bus 0 the crs resources used by other busses.
Marcel Apfelbaum
marcel at redhat.com
Mon Feb 16 10:54:05 CET 2015
If multiple root busses are used, root bus 0 cannot use all the
pci holes ranges. Remove the IO/mem ranges used by the other
primary busses.
Signed-off-by: Marcel Apfelbaum <marcel at redhat.com>
---
hw/i386/acpi-build.c | 85 ++++++++++++++++++++++++++++++++++++++++++++--------
1 file changed, 73 insertions(+), 12 deletions(-)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 0822a20..b2b0036 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -870,6 +870,9 @@ build_ssdt(AcpiAml *table_aml, GArray *linker,
int i;
PciRangeQ io_ranges = QLIST_HEAD_INITIALIZER(io_ranges);
PciRangeQ mem_ranges = QLIST_HEAD_INITIALIZER(mem_ranges);
+ PciMemoryRange range;
+ PciRangeEntry *entry;
+ int root_bus_limit = 0xFF;
/* The current AML generator can cover the APIC ID range [0..255],
* inclusive, for VCPU hotplug. */
@@ -897,6 +900,10 @@ build_ssdt(AcpiAml *table_aml, GArray *linker,
continue;
}
+ if (bus_info->bus < root_bus_limit) {
+ root_bus_limit = bus_info->bus - 1;
+ }
+
scope = acpi_scope("\\_SB");
dev = acpi_device("PC%.02X", (uint8_t)bus_info->bus);
aml_append(&dev, acpi_name_decl("_UID",
@@ -911,8 +918,6 @@ build_ssdt(AcpiAml *table_aml, GArray *linker,
aml_append(&ssdt, scope);
}
- pci_range_list_free(&io_ranges);
- pci_range_list_free(&mem_ranges);
qapi_free_PciInfoList(info_list);
}
@@ -921,26 +926,79 @@ build_ssdt(AcpiAml *table_aml, GArray *linker,
crs = acpi_resource_template();
aml_append(&crs,
acpi_word_bus_number(acpi_min_fixed, acpi_max_fixed, acpi_pos_decode,
- 0x0000, 0x0000, 0x00FF, 0x0000, 0x0100));
+ 0x0000, 0x0, root_bus_limit,
+ 0x0000, root_bus_limit + 1));
+
aml_append(&crs, acpi_io(acpi_decode16, 0x0CF8, 0x0CF8, 0x01, 0x08));
aml_append(&crs,
acpi_word_io(acpi_min_fixed, acpi_max_fixed,
acpi_pos_decode, acpi_entire_range,
0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
- aml_append(&crs,
- acpi_word_io(acpi_min_fixed, acpi_max_fixed,
- acpi_pos_decode, acpi_entire_range,
- 0x0000, 0x0D00, 0xFFFF, 0x0000, 0xF300));
+
+ /* prepare PCI IO ranges */
+ range.base = 0x0D00;
+ range.limit = 0xFFFF;
+ if (QLIST_EMPTY(&io_ranges)) {
+ aml_append(&crs,
+ acpi_word_io(acpi_min_fixed, acpi_max_fixed,
+ acpi_pos_decode, acpi_entire_range,
+ 0x0000, range.base, range.limit,
+ 0x0000, range.limit - range.base + 1));
+ } else {
+ QLIST_FOREACH(entry, &io_ranges, entry) {
+ if (range.base < entry->base) {
+ aml_append(&crs,
+ acpi_word_io(acpi_min_fixed, acpi_max_fixed,
+ acpi_pos_decode, acpi_entire_range,
+ 0x0000, range.base, entry->base - 1,
+ 0x0000, entry->base - range.base));
+ }
+ range.base = entry->limit + 1;
+ if (!QLIST_NEXT(entry, entry)) {
+ aml_append(&crs,
+ acpi_word_io(acpi_min_fixed, acpi_max_fixed,
+ acpi_pos_decode, acpi_entire_range,
+ 0x0000, range.base, range.limit,
+ 0x0000, range.limit - range.base + 1));
+ }
+ }
+ }
+
aml_append(&crs,
acpi_dword_memory(acpi_pos_decode, acpi_min_fixed, acpi_max_fixed,
acpi_cacheable, acpi_ReadWrite,
0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
- aml_append(&crs,
- acpi_dword_memory(acpi_pos_decode, acpi_min_fixed, acpi_max_fixed,
- acpi_non_cacheable, acpi_ReadWrite,
- 0, pci->w32.begin, pci->w32.end - 1, 0,
- pci->w32.end - pci->w32.begin));
+
+ /* prepare PCI memory ranges */
+ range.base = pci->w32.begin;
+ range.limit = pci->w32.end - 1;
+ if (QLIST_EMPTY(&mem_ranges)) {
+ aml_append(&crs,
+ acpi_dword_memory(acpi_pos_decode, acpi_min_fixed, acpi_max_fixed,
+ acpi_non_cacheable, acpi_ReadWrite,
+ 0, range.base, range.limit,
+ 0, range.limit - range.base + 1));
+ } else {
+ QLIST_FOREACH(entry, &mem_ranges, entry) {
+ if (range.base < entry->base) {
+ aml_append(&crs,
+ acpi_dword_memory(acpi_pos_decode, acpi_min_fixed, acpi_max_fixed,
+ acpi_non_cacheable, acpi_ReadWrite,
+ 0, range.base, entry->base - 1,
+ 0, entry->base - range.base));
+ }
+ range.base = entry->limit + 1;
+ if (!QLIST_NEXT(entry, entry)) {
+ aml_append(&crs,
+ acpi_dword_memory(acpi_pos_decode, acpi_min_fixed, acpi_max_fixed,
+ acpi_non_cacheable, acpi_ReadWrite,
+ 0, range.base, range.limit,
+ 0, range.base - range.limit + 1));
+ }
+ }
+ }
+
if (pci->w64.begin) {
aml_append(&crs,
acpi_qword_memory(acpi_pos_decode, acpi_min_fixed, acpi_max_fixed,
@@ -950,6 +1008,9 @@ build_ssdt(AcpiAml *table_aml, GArray *linker,
}
aml_append(&scope, acpi_name_decl("_CRS", crs));
+ pci_range_list_free(&io_ranges);
+ pci_range_list_free(&mem_ranges);
+
/* reserve PCIHP resources */
if (pm->pcihp_io_len) {
dev = acpi_device("PHPR");
--
2.1.0
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