[SeaBIOS] [PATCH 1/5] piix: add and use dev-piix.h
Paolo Bonzini
kevin at koconnor.net
Sat May 31 03:06:59 CEST 2014
Move all definitions for PIIX registers to a single header file,
like there is one already for Q35, and make the naming more
consistent.
Signed-off-by: Paolo Bonzini <pbonzini at redhat.com>
---
src/fw/acpi.c | 18 ++++++------------
src/fw/dev-piix.h | 27 +++++++++++++++++++++++++++
src/fw/pciinit.c | 13 +++++++------
src/fw/shadow.c | 3 +--
src/fw/smm.c | 9 +++------
5 files changed, 44 insertions(+), 26 deletions(-)
create mode 100644 src/fw/dev-piix.h
diff --git a/src/fw/acpi.c b/src/fw/acpi.c
index 733ca4d..47e4c07 100644
--- a/src/fw/acpi.c
+++ b/src/fw/acpi.c
@@ -9,6 +9,7 @@
#include "byteorder.h" // cpu_to_le16
#include "config.h" // CONFIG_*
#include "dev-q35.h"
+#include "dev-piix.h"
#include "hw/pci.h" // pci_find_init_device
#include "hw/pci_ids.h" // PCI_VENDOR_ID_INTEL
#include "hw/pci_regs.h" // PCI_INTERRUPT_LINE
@@ -38,31 +39,24 @@ build_header(struct acpi_table_header *h, u32 sig, int len, u8 rev)
h->checksum -= checksum(h, len);
}
-#define PIIX4_ACPI_ENABLE 0xf1
-#define PIIX4_ACPI_DISABLE 0xf0
-#define PIIX4_GPE0_BLK 0xafe0
-#define PIIX4_GPE0_BLK_LEN 4
-
-#define PIIX4_PM_INTRRUPT 9 // irq 9
-
static void piix4_fadt_setup(struct pci_device *pci, void *arg)
{
struct fadt_descriptor_rev1 *fadt = arg;
fadt->model = 1;
fadt->reserved1 = 0;
- fadt->sci_int = cpu_to_le16(PIIX4_PM_INTRRUPT);
+ fadt->sci_int = cpu_to_le16(PIIX_PM_INTRRUPT);
fadt->smi_cmd = cpu_to_le32(PORT_SMI_CMD);
- fadt->acpi_enable = PIIX4_ACPI_ENABLE;
- fadt->acpi_disable = PIIX4_ACPI_DISABLE;
+ fadt->acpi_enable = PIIX_ACPI_ENABLE;
+ fadt->acpi_disable = PIIX_ACPI_DISABLE;
fadt->pm1a_evt_blk = cpu_to_le32(acpi_pm_base);
fadt->pm1a_cnt_blk = cpu_to_le32(acpi_pm_base + 0x04);
fadt->pm_tmr_blk = cpu_to_le32(acpi_pm_base + 0x08);
- fadt->gpe0_blk = cpu_to_le32(PIIX4_GPE0_BLK);
+ fadt->gpe0_blk = cpu_to_le32(PIIX_GPE0_BLK);
fadt->pm1_evt_len = 4;
fadt->pm1_cnt_len = 2;
fadt->pm_tmr_len = 4;
- fadt->gpe0_blk_len = PIIX4_GPE0_BLK_LEN;
+ fadt->gpe0_blk_len = PIIX_GPE0_BLK_LEN;
fadt->plvl2_lat = cpu_to_le16(0xfff); // C2 state not supported
fadt->plvl3_lat = cpu_to_le16(0xfff); // C3 state not supported
/* WBINVD + PROC_C1 + SLP_BUTTON + RTC_S4 + USE_PLATFORM_CLOCK */
diff --git a/src/fw/dev-piix.h b/src/fw/dev-piix.h
new file mode 100644
index 0000000..c6dce03
--- /dev/null
+++ b/src/fw/dev-piix.h
@@ -0,0 +1,27 @@
+#ifndef __DEV_PIIX_H
+#define __DEV_PIIX_H
+
+#define I440FX_PAM0 0x59
+#define I440FX_SMRAM 0x72
+
+#define PIIX_PMBASE 0x40
+#define PIIX_PMREGMISC 0x80
+#define PIIX_SMBHSTBASE 0x90
+#define PIIX_SMBHSTCFG 0xd2
+#define PIIX_DEVACTB 0x58
+#define PIIX_DEVACTB_APMC_EN (1 << 25)
+
+#define PIIX_PORT_ELCR1 0x4d0
+#define PIIX_PORT_ELCR2 0x4d1
+
+/* ICH9 PM I/O registers */
+#define PIIX_GPE0_BLK 0xafe0
+#define PIIX_GPE0_BLK_LEN 4
+
+/* FADT ACPI_ENABLE/ACPI_DISABLE */
+#define PIIX_ACPI_ENABLE 0xf1
+#define PIIX_ACPI_DISABLE 0xf0
+
+#define PIIX_PM_INTRRUPT 9 // irq 9
+
+#endif // dev-piix.h
diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c
index 2e6382f..0ad548f 100644
--- a/src/fw/pciinit.c
+++ b/src/fw/pciinit.c
@@ -8,6 +8,7 @@
#include "byteorder.h" // le64_to_cpu
#include "config.h" // CONFIG_*
#include "dev-q35.h" // Q35_HOST_BRIDGE_PCIEXBAR_ADDR
+#include "dev-piix.h" // PIIX_*
#include "hw/ata.h" // PORT_ATA1_CMD_BASE
#include "hw/pci.h" // pci_config_readl
#include "hw/pci_ids.h" // PCI_VENDOR_ID_INTEL
@@ -152,8 +153,8 @@ static void piix_isa_bridge_setup(struct pci_device *pci, void *arg)
/* activate irq remapping in PIIX */
pci_config_writeb(pci->bdf, 0x60 + i, irq);
}
- outb(elcr[0], 0x4d0);
- outb(elcr[1], 0x4d1);
+ outb(elcr[0], PIIX_PORT_ELCR1);
+ outb(elcr[1], PIIX_PORT_ELCR2);
dprintf(1, "PIIX3/PIIX4 init: elcr=%02x %02x\n", elcr[0], elcr[1]);
}
@@ -229,10 +230,10 @@ static void piix4_pm_config_setup(u16 bdf)
// acpi sci is hardwired to 9
pci_config_writeb(bdf, PCI_INTERRUPT_LINE, 9);
- pci_config_writel(bdf, 0x40, acpi_pm_base | 1);
- pci_config_writeb(bdf, 0x80, 0x01); /* enable PM io space */
- pci_config_writel(bdf, 0x90, (acpi_pm_base + 0x100) | 1);
- pci_config_writeb(bdf, 0xd2, 0x09); /* enable SMBus io space */
+ pci_config_writel(bdf, PIIX_PMBASE, acpi_pm_base | 1);
+ pci_config_writeb(bdf, PIIX_PMREGMISC, 0x01); /* enable PM io space */
+ pci_config_writel(bdf, PIIX_SMBHSTBASE, (acpi_pm_base + 0x100) | 1);
+ pci_config_writeb(bdf, PIIX_SMBHSTCFG, 0x09); /* enable SMBus io space */
}
static int PiixPmBDF = -1;
diff --git a/src/fw/shadow.c b/src/fw/shadow.c
index 82d6753..4f00006 100644
--- a/src/fw/shadow.c
+++ b/src/fw/shadow.c
@@ -7,6 +7,7 @@
#include "config.h" // CONFIG_*
#include "dev-q35.h" // PCI_VENDOR_ID_INTEL
+#include "dev-piix.h" // I440FX_PAM0
#include "hw/pci.h" // pci_config_writeb
#include "hw/pci_ids.h" // PCI_VENDOR_ID_INTEL
#include "hw/pci_regs.h" // PCI_VENDOR_ID
@@ -20,8 +21,6 @@
// On the emulators, the bios at 0xf0000 is also at 0xffff0000
#define BIOS_SRC_OFFSET 0xfff00000
-#define I440FX_PAM0 0x59
-
// Enable shadowing and copy bios.
static void
__make_bios_writable_intel(u16 bdf, u32 pam0)
diff --git a/src/fw/smm.c b/src/fw/smm.c
index 0f59f20..20bf631 100644
--- a/src/fw/smm.c
+++ b/src/fw/smm.c
@@ -7,6 +7,7 @@
#include "config.h" // CONFIG_*
#include "dev-q35.h"
+#include "dev-piix.h"
#include "hw/pci.h" // pci_config_writel
#include "hw/pci_ids.h" // PCI_VENDOR_ID_INTEL
#include "hw/pci_regs.h" // PCI_DEVICE_ID
@@ -86,16 +87,12 @@ smm_relocate_and_restore(void)
wbinvd();
}
-#define I440FX_SMRAM 0x72
-#define PIIX_DEVACTB 0x58
-#define PIIX_APMC_EN (1 << 25)
-
// This code is hardcoded for PIIX4 Power Management device.
static void piix4_apmc_smm_setup(int isabdf, int i440_bdf)
{
/* check if SMM init is already done */
u32 value = pci_config_readl(isabdf, PIIX_DEVACTB);
- if (value & PIIX_APMC_EN)
+ if (value & PIIX_DEVACTB_APMC_EN)
return;
/* enable the SMM memory window */
@@ -104,7 +101,7 @@ static void piix4_apmc_smm_setup(int isabdf, int i440_bdf)
smm_save_and_copy();
/* enable SMI generation when writing to the APMC register */
- pci_config_writel(isabdf, PIIX_DEVACTB, value | PIIX_APMC_EN);
+ pci_config_writel(isabdf, PIIX_DEVACTB, value | PIIX_DEVACTB_APMC_EN);
smm_relocate_and_restore();
--
1.9.3
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