[SeaBIOS] [PATCH 3/4] romlayout: Use .code16 not .code16gcc
David Woodhouse
dwmw2 at infradead.org
Tue Jun 3 18:28:49 CEST 2014
There's no need to use .code16gcc where we are writing assembler code
explicitly. It only affects word-size-ambiguous instructions, and we
should just be explicit. And we are.
Signed-off-by: David Woodhouse <David.Woodhouse at intel.com>
---
src/romlayout.S | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/src/romlayout.S b/src/romlayout.S
index 57e8bcc..9c2719e 100644
--- a/src/romlayout.S
+++ b/src/romlayout.S
@@ -21,7 +21,7 @@
// %edx = return location (in 32bit mode)
// Clobbers: ecx, flags, segment registers, cr0, idt/gdt
DECLFUNC transition32
- .code16gcc
+ .code16
transition32:
movl %eax, %ecx
@@ -102,7 +102,7 @@ transition16big:
ljmpw $SEG32_MODE16BIG_CS, $1f
- .code16gcc
+ .code16
1:
// Disable protected mode
movl %cr0, %eax
@@ -145,7 +145,7 @@ __call16big:
jmp transition16big
// Make call.
- .code16gcc
+ .code16
1: movl $_zonelow_seg, %edx // Adjust %ds, %ss, and %esp
movl %edx, %ds
movzwl StackSeg, %edx
@@ -177,7 +177,7 @@ __call16big:
// Far call a 16bit function from 16bit mode with a specified cpu register state
// %eax = address of struct bregs, %edx = segment of struct bregs
// Clobbers: %e[bc]x, %e[ds]i, flags
- .code16gcc
+ .code16
DECLFUNC __farcall16
__farcall16:
// Save %edx/%eax, %ebp
@@ -372,7 +372,7 @@ entry_pcibios32:
popfl
lretl
- .code16gcc
+ .code16
DECLFUNC entry_pcibios16
entry_pcibios16:
ENTRY_ARG handle_pcibios
@@ -421,7 +421,7 @@ entry_elf:
movl $BUILD_STACK_ADDR, %esp
ljmpl $SEG32_MODE32_CS, $_cfunc32flat_handle_post
- .code16gcc
+ .code16
// UEFI Compatibility Support Module (CSM) entry point
EXPORTFUNC entry_csm
@@ -453,7 +453,7 @@ entry_csm:
__csm_return:
movl $1f, %edx
jmp transition16big
- .code16gcc
+ .code16
// Switch back to original stack
1: movzwl BREGS_code+2(%eax), %edx
--
1.9.3
--
David Woodhouse Open Source Technology Centre
David.Woodhouse at intel.com Intel Corporation
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