[SeaBIOS] [PATCH v4] Update EFI_COMPATIBILITY16_TABLE to match 0.98 spec update
David Woodhouse
dwmw2 at infradead.org
Mon Jun 2 15:00:14 CEST 2014
Unless CONFIG_MALLOC_UPPERMEMORY is turned off, we expect to use the
space between the top of option ROMs and the bottom of our own BIOS code
as a stack. OVMF was previously marking the whole region from 0xC0000 to
0xFFFFF read-only before invoking our Legacy16Boot method. Read-only
stack considered harmful.
Version 0.98 of the CSM spec adds the UmaAddress and UmaSize fields which
allow the CSM to specify a memory region that needs to be writeable, so
provide that information.
Signed-off-by: David Woodhouse <David.Woodhouse at intel.com>
---
src/fw/csm.c | 6 ++++++
src/std/LegacyBios.h | 20 ++++++++++++++++++++
2 files changed, 26 insertions(+)
diff --git a/src/fw/csm.c b/src/fw/csm.c
index a44ed26..7cdb398 100644
--- a/src/fw/csm.c
+++ b/src/fw/csm.c
@@ -46,8 +46,14 @@ extern void __csm_return(struct bregs *regs) __noreturn;
static void
csm_return(struct bregs *regs)
{
+ u32 rommax = rom_get_max();
+ extern u8 final_readonly_start[];
+
dprintf(3, "handle_csm returning AX=%04x\n", regs->ax);
+ csm_compat_table.UmaAddress = rommax;
+ csm_compat_table.UmaSize = (u32)final_readonly_start - rommax;
+
PICMask = pic_irqmask_read();
__csm_return(regs);
}
diff --git a/src/std/LegacyBios.h b/src/std/LegacyBios.h
index cf0c3c5..5170c37 100644
--- a/src/std/LegacyBios.h
+++ b/src/std/LegacyBios.h
@@ -228,6 +228,26 @@ typedef struct {
/// Maximum PCI bus number assigned.
///
UINT8 LastPciBus;
+
+ ///
+ /// Start address of UMB RAM
+ ///
+ UINT32 UmaAddress;
+
+ ///
+ /// Size of UMB RAM
+ ///
+ UINT32 UmaSize;
+
+ ///
+ /// Start address of persistent allocation in high (>1MiB) memory
+ ///
+ UINT32 HiPermanentMemoryAddress;
+
+ ///
+ /// Size of persistent allocation in high (>1MiB) memory
+ ///
+ UINT32 HiPermanentMemorySize;
} EFI_COMPATIBILITY16_TABLE;
///
--
1.9.0
--
dwmw2
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