[SeaBIOS] [Qemu-devel] [PATCH] hw/pci: reserve IO and mem for pci-2-pci bridges with no devices attached

[Michael S. Tsirkin]

On Tue, Apr 08, 2014 at 08:05:23AM +0200, Gerd Hoffmann wrote:
> On Mo, 2014-04-07 at 16:34 +0300, Michael S. Tsirkin wrote:
> > On Mon, Apr 07, 2014 at 02:44:06PM +0200, Gerd Hoffmann wrote:
> > >   Hi,
> > > 
> > > > > +        u8 shpc_cap = pci_find_capability(s->bus_dev, PCI_CAP_ID_SHPC);
> > > 
> > > > One thing I'd do is maybe check that the relevant memory type is
> > > > enabled in the bridge (probably just by writing fff to base and reading
> > > > it back).
> > > 
> > > > This will give hypervisors an option to avoid wasting resources:
> > > > e.g. it's uncommon for express devices to claim IO.
> > > 
> > > I don't think we'll need that for the SHPC bridge.
> > 
> > Why not?
> 
> With typical use cases for the shpc bridge you likely need the io window
> anyway.

That won't be true after virtio 1.0 is out.

> > I'm referring to this text in the bridge specification:
> > 
> > 	The I/O Base and I/O Limit registers are optional and define an address
> > 	range that is used
> > 	by the bridge to determine when to forward I/O transactions from one
> > 	interface to the
> > 	other.
> > 	If a bridge does not implement an I/O address range, then both the I/O
> > 	Base and I/O
> > 	Limit registers must be implemented as read-only registers that return
> > 	zero when read. If a
> > 	bridge supports an I/O address range, then these registers must be
> > 	initialized by
> > 	configuration software so default states are not specified.
> > 
> > So we should probe bridge for I/O support before wasting I/O resources on it.
> 
> Yes, makes sense from a correctness point of view.

So that's all I'm arguing for, for now: let's implement the spec
correctly.
Whether we should emulate such devices is a separate question.

> I suspect you'll have a hard time to find such bridges in the x86 world
> though, so I'm not sure it is a good idea to emulate this in qemu.
> Guests might not handle it correctly.

We'll have to test this.
The handling is mostly done by BIOS so I don't expect a lot of problems.

> > > For express it indeed makes sense to avoid claiming IO address space.
> > > I'd try to find something more automatic though, where you don't need
> > > some kind of "disable io for this express port" config option.
> > 
> > Won't same trick as above work?
> 
> Yes, it will work.
> 
> But as we probably want support io on express devices (because it is
> used in practice, even though being strongly discouraged in the pci
> express specs).  So doing it that way would require a config switch on
> the qemu side to turn on/off io address space support for express
> switches/ports.
> 
> cheers,
>   Gerd

True but I don't see a way around this anyway.
At least this way we won't need PV.


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MST