[SeaBIOS] [PATCH 6/6] pci: map 64-bit BARs at location provided by emulator

[Gerd Hoffmann]

Currently 64-bit PCI BARs are unconditionally mapped by BIOS right
over 4G + RamSizeOver4G location, which doesn't allow to reserve
extra space before 64-bit PCI window. For memory hotplug an extra
RAM space might be reserved after present 64-bit RAM end and BIOS
should map 64-bit PCI BARs after it.

Introduce "etc/reserved-memory-end" romfile to provide BIOS a hint
where it should start mapping of 64-bit PCI BARs. If romfile is
missing, BIOS reverts to legacy behavior and starts mapping after
high memory.

Based-on-patch-by: Igor Mammedov <imammedo at redhat.com>
Signed-off-by: Gerd Hoffmann <kraxel at redhat.com>
---
 src/fw/pciinit.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c
index 3de0c7e..654697d 100644
--- a/src/fw/pciinit.c
+++ b/src/fw/pciinit.c
@@ -19,6 +19,8 @@
 #include "string.h" // memset
 #include "util.h" // pci_setup
 #include "x86.h" // outb
+#include "byteorder.h" // le64_to_cpu
+#include "romfile.h" // romfile_loadint
 
 #define PCI_DEVICE_MEM_MIN    (1<<12)  // 4k == page size
 #define PCI_BRIDGE_MEM_MIN    (1<<21)  // 2M == hugepage size
@@ -788,7 +790,9 @@ static void pci_bios_map_devices(struct pci_bus *busses)
         u64 align_mem = pci_region_align(&r64_mem);
         u64 align_pref = pci_region_align(&r64_pref);
 
-        r64_mem.base = 0x100000000LL + RamSizeOver4G;
+        r64_mem.base = le64_to_cpu(romfile_loadint("etc/reserved-memory-end", 0));
+        if (r64_mem.base < 0x100000000LL + RamSizeOver4G)
+            r64_mem.base = 0x100000000LL + RamSizeOver4G;
         r64_mem.base = ALIGN(r64_mem.base, align_mem);
         r64_mem.base = ALIGN(r64_mem.base, (1LL<<30));    // 1G hugepage
         r64_pref.base = r64_mem.base + sum_mem;
-- 
1.8.3.1