[SeaBIOS] [PATCH] Seabios: allow mapping of multiple PCI option ROMs to one

[Dave Frodin]

All, 
This is a patch that reproduces the vendor ID mapping that is done in 
coreboot in the various AMD northbridge's. The coreboot mapping is only 
useful if coreboot is used to run the vga bios. If seabios is the payload 
then most coreboot configs leave the vga bios init for it. 



>From 5b7f2ba9f43fbc67a81a2449d8bbd3d2f6e530aa Mon Sep 17 00:00:00 2001 
From: Dave Frodin <dave.frodin at se-eng.com> 
Date: Tue, 7 May 2013 13:51:56 -0600 
Subject: [PATCH] Seabios: allow mapping of multiple PCI option ROMs to one 

This feature was added to allow mapping multiple different 
PCI graphics vendor/device IDs to a single ID. The intent is 
to have the coreboot mainboard define its VGA_BIOS_ID as the 
ID that is present in the actual VGA BIOS. The PCI ID of the 
graphics device would then be mapped to that ID. 

Change-Id: Id06a1c9730546070146932a4dc8ab8229c4a59b9 
Signed-off-by: Dave Frodin <dave.frodin at se-eng.com> 
--- 
src/optionroms.c | 69 +++++++++++++++++++++++++++++++++++++++++++++++++++++- 
1 files changed, 68 insertions(+), 1 deletions(-) 

diff --git a/src/optionroms.c b/src/optionroms.c 
index 00697b2..bf1e977 100644 
--- a/src/optionroms.c 
+++ b/src/optionroms.c 
@@ -154,7 +154,6 @@ getRomPriority(u64 *sources, struct rom_header *rom, int instance) 
return bootprio_find_named_rom(file->name, instance); 
} 

- 
/**************************************************************** 
* Roms in CBFS 
****************************************************************/ 
@@ -174,11 +173,79 @@ deploy_romfile(struct romfile_s *file) 
return rom; 
} 

+/* Allow mapping of multiple different PCI IDs to a single ID. A single AMD 
+ * VGA BIOS will quite often be used on hardware that reports different 
+ * PCI graphics IDs. This allows a mainboard to have a single definition 
+ * (which would match the ID in the VGA BIOS) yet would support multiple 
+ * CPU IDs. 
+ */ 
+static u32 
+map_oprom_vendev(u32 vendev) 
+{ 
+ u32 new_vendev = vendev; 
+ 
+ switch (vendev) { 
+ case 0x10029803: // Family14 
+ case 0x10029804: 
+ case 0x10029805: 
+ case 0x10029806: 
+ case 0x10029807: 
+ case 0x10029808: 
+ case 0x10029809: 
+ new_vendev = 0x10029802; 
+ break; 
+ case 0x10029901: // Family15tn 
+ case 0x10029903: 
+ case 0x10029904: 
+ case 0x10029906: 
+ case 0x10029907: 
+ case 0x10029908: 
+ case 0x1002990A: 
+ case 0x10029910: 
+ case 0x10029913: 
+ case 0x10029917: 
+ case 0x10029918: 
+ case 0x10029919: 
+ case 0x10029990: 
+ case 0x10029991: 
+ case 0x10029992: 
+ case 0x10029993: 
+ case 0x10029994: 
+ case 0x100299A0: 
+ case 0x100299A2: 
+ case 0x100299A4: 
+ new_vendev = 0x10029900; 
+ break; 
+ case 0x10029831: // Family16kb 
+ case 0x10029832: 
+ case 0x10029833: 
+ case 0x10029834: 
+ case 0x10029835: 
+ case 0x10029836: 
+ case 0x10029837: 
+ case 0x10029839: 
+ case 0x1002983D: 
+ new_vendev = 0x10029830; 
+ break; 
+ default: 
+ break; 
+ } 
+ if (vendev != new_vendev) 
+ dprintf(1, "Mapping PCI device %8x to %8x\n",vendev, new_vendev); 
+ return new_vendev; 
+} 
+ 
// Check if an option rom is at a hardcoded location or in CBFS. 
static struct rom_header * 
lookup_hardcode(struct pci_device *pci) 
{ 
char fname[17]; 
+ u32 vendev_mapped; 
+ 
+ vendev_mapped = map_oprom_vendev((pci->vendor << 16) | pci->device); 
+ pci->vendor = vendev_mapped >> 16; 
+ pci->device = vendev_mapped & 0xFFFF; 
+ 
snprintf(fname, sizeof(fname), "pci%04x,%04x.rom" 
, pci->vendor, pci->device); 
struct romfile_s *file = romfile_find(fname); 
-- 
1.7.9 

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