[SeaBIOS] [RFC PATCH] ich9: Fix interrupt routing

[Alex Williamson]

It's really not that arbitrary how we translate slot:pin to pirq
register.  We not only need to match the ACPI table we provide
to the guest, but the BIOS has dependencies for programming PCI
interrupt line registers for boot ROMs that use interrupts.  If
we don't match the slot:pin to pirq of PIIX then we need to come
up with our own mapping function.  NB. We might need our own map
function anyway because slots 25-31 do their own thing so BIOS
interrupt line mapping will still fail (no interrupt mode boot
ROMs below express ports).

Signed-off-by: Alex Williamson <alex.williamson at redhat.com>
---
 hw/lpc_ich9.c             |    9 ++++-----
 pc-bios/q35-acpi-dsdt.aml |  Bin
 2 files changed, 4 insertions(+), 5 deletions(-)

Binary not included.  This includes the required Qemu changes
to match the slot:pin updates in seabios.

diff --git a/hw/lpc_ich9.c b/hw/lpc_ich9.c
index 16843d7..7b9e348 100644
--- a/hw/lpc_ich9.c
+++ b/hw/lpc_ich9.c
@@ -109,17 +109,16 @@ static void ich9_cc_init(ICH9LPCState *lpc)
     int intx;
 
     /* the default irq routing is arbitrary as long as it matches with
-     * acpi irq routing table.
-     * The one that is incompatible with piix_pci(= bochs) one is
-     * intentionally chosen to let the users know that the different
-     * board is used.
+     * acpi irq routing table and BIOS.
      *
      * int[A-D] -> pirq[E-F]
      * avoid pirq A-D because they are used for pci express port
+     * Keep the same slot rotation as piix or the bios won't know
+     * how to program PCI interrupt line registers for boot ROMs.
      */
     for (slot = 0; slot < PCI_SLOT_MAX; slot++) {
         for (intx = 0; intx < PCI_NUM_PINS; intx++) {
-            lpc->irr[slot][intx] = (slot + intx) % 4 + 4;
+            lpc->irr[slot][intx] = ((slot + intx - 1) & 3) + 4;
         }
     }
     ich9_cc_update(lpc);