[SeaBIOS] [PATCH 2/3] POST: Move cpu caching and dma setup to platform_hardware_setup().

[Kevin O'Connor]

The CPU cache is enabled and DMA is disabled on all real-world POST
entry situations, so no need to do this in the low-level "pre-init"
phase.  Instead, move it to the platform hardware setup stage.

Signed-off-by: Kevin O'Connor <kevin at koconnor.net>
---
 src/post.c   | 12 ++++++------
 src/resume.c |  4 ++--
 src/util.h   |  2 +-
 3 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/src/post.c b/src/post.c
index 56df90c..e5435b1 100644
--- a/src/post.c
+++ b/src/post.c
@@ -144,6 +144,12 @@ device_hardware_setup(void)
 static void
 platform_hardware_setup(void)
 {
+    // Enable CPU caching
+    setcr0(getcr0() & ~(CR0_CD|CR0_NW));
+
+    // Make sure legacy DMA isn't running.
+    dma_setup();
+
     // Init base pc hardware.
     pic_setup();
     timer_setup();
@@ -304,12 +310,6 @@ preinit(void)
     HaveRunPost = 1;
     outb_cmos(0, CMOS_RESET_CODE);
 
-    // Enable CPU caching
-    setcr0(getcr0() & ~(CR0_CD|CR0_NW));
-
-    // Make sure legacy DMA isn't running.
-    dma_preinit();
-
     // Check if we are running under Xen.
     xen_preinit();
 
diff --git a/src/resume.c b/src/resume.c
index 99265cd..ffc84fc 100644
--- a/src/resume.c
+++ b/src/resume.c
@@ -19,7 +19,7 @@ int HaveRunPost VAR16VISIBLE;
 
 // Reset DMA controller
 void
-dma_preinit(void)
+dma_setup(void)
 {
     // first reset the DMA controllers
     outb(0, PORT_DMA1_MASTER_CLEAR);
@@ -40,7 +40,7 @@ handle_resume(void)
     outb_cmos(0, CMOS_RESET_CODE);
     dprintf(1, "In resume (status=%d)\n", status);
 
-    dma_preinit();
+    dma_setup();
 
     switch (status) {
     case 0x01 ... 0x04:
diff --git a/src/util.h b/src/util.h
index eb35d02..88f5905 100644
--- a/src/util.h
+++ b/src/util.h
@@ -354,7 +354,7 @@ void disable_bootsplash(void);
 
 // resume.c
 extern int HaveRunPost;
-void dma_preinit(void);
+void dma_setup(void);
 
 // pnpbios.c
 #define PNP_SIGNATURE 0x506e5024 // $PnP
-- 
1.7.11.7