[SeaBIOS] [Qemu-devel] [edk2] (PAM stuff) reset doesn't work on OVMF + SeaBIOS CSM

[Laszlo Ersek]

On 02/19/13 16:29, David Woodhouse wrote:
> On Mon, 2013-02-18 at 17:37 -0500, Kevin O'Connor wrote:
>> The ACPI v2 spec describes a "hard" reset register.  SeaBIOS could
>> extract it from the FADT and then use it.  Of course, we'd probably
>> want to update the QEMU ACPI tables to implement ACPI v2 then.
>
> This sounded great until I actually came to implement it.
>
> The PIIX reset at 0xcf9 requires *two* writes; one to set the reset type
> and then a second write with bit 2 set to actually do the reset.
>
> The ACPI RESET_REG definition only allows for *one* value to be written.
>
> Is that because the PIIX will actually do a hard reset when you write
> 0x06 to it *anyway*, despite theoretically saying that you should write
> 0x02 first? Or is the ACPI definition of RESET_REG simply incapable of
> being used on the PIIX?

The linux kernel actually considers BOOT_ACPI and BOOT_CF9 separate
things; see

- native_machine_emergency_restart() [arch/x86/kernel/reboot.c],
- acpi_reboot() [drivers/acpi/reboot.c],
- acpi_reset() [drivers/acpi/acpica/hwxface.c].

BOOT_ACPI looks like a single write in any case (io space, memory, pci
config).

Funnily enough, on my Thinkpad (
  acpidump --table FACP --binary -o fadt.aml
  iasl -d fadt.aml
):

  /*
   * Intel ACPI Component Architecture
   * AML Disassembler version 20090123
   *
   * Disassembly of fadt.aml, Tue Feb 19 17:13:43 2013
   *
   * ACPI Data Table [FACP]
   *
   * Format: [HexOffset DecimalOffset ByteLength]  FieldName : FieldValue
   */

  [000h 000  4]                    Signature : "FACP"    /* Fixed ACPI Description Table */

  [070h 112  4]        Flags (decoded below) : 0000C2AD
               Reset Register Supported (V2) : 0

  [074h 116 12]               Reset Register : <Generic Address Structure>
  [074h 116  1]                     Space ID : 01 (SystemIO)
  [075h 117  1]                    Bit Width : 08
  [076h 118  1]                   Bit Offset : 00
  [077h 119  1]                 Access Width : 00
  [078h 120  8]                      Address : 0000000000000CF9
  [080h 128  1]         Value to cause reset : 06

Same on my HP Z400. "Reset register is not supported, but you could
still write 6 to 0xcf9" :)

I'd say "6 to 0xCF9" is good enough; rcr_write() in qemu is OK with it
too (including your patch at
<http://thread.gmane.org/gmane.comp.emulators.qemu/195351/focus=195387>.)

Laszlo