[SeaBIOS] [edk2] (PAM stuff) reset doesn't work on OVMF + SeaBIOS CSM

[David Woodhouse]

On Mon, 2013-02-18 at 10:40 +0000, David Woodhouse wrote:
> On Sat, 2013-02-16 at 02:37 +0100, Laszlo Ersek wrote:
> > I give up. Thanks for the help & sorry about spamming three lists.
> 
> I've managed to reproduce this on a clean F18 system. This is the stock
> qemu 1.2.2-6.fc18 on kernel 3.7.6-201.fc18.x86_64 with a newly-installed
> Fedora 18 VM in the guest.
> 
> qemu-system-x86_64 -enable-kvm -cdrom F18boot.iso -serial mon:stdio -bios OVMF.fd
> 
> On my laptop where I'd been doing most of my testing, even after running
> 'yum distro-sync qemu\*' to get back to the stock qemu, I still can't
> reproduce the issue. They are both running the *same* kernel.
> 
> I'll try reverting a whole bunch of other stuff that ought to be
> irrelevant to the stock distro packages, and see if/when it breaks...

I cannot make these two machines behave consistently. I have absolutely
no clue what is going on here.

At reset, the PAM regions are all set to '1' (read only). So the CSM
should reside in RAM at 0xffff0 but THAT SHOULDN'T MATTER. After a reset
we should be running from 0xfffffff0 and there's unconditionally ROM
there, isn't there?

Nevertheless, on my workstation as on yours, we do seem to end up
executing from the CSM in RAM when we reset. But on my laptop, it
executes the *ROM* as it should.

This patch 'fixes' it, and I think it might even be correct in itself,
but I don't think it's a correct fix for the problem we're discussing.
And I certainly want to know what's different on my laptop that makes it
work *without* this patch.

Either there's some weirdness with setting the high CS base address, on
CPU reset. Or perhaps the contents of the memory region at 0xfffffff0
have *really* been changed along with the sub-1MiB range. Or maybe the
universe just hates us...


diff --git a/hw/piix_pci.c b/hw/piix_pci.c
index 6c77e49..6dcf1c5 100644
--- a/hw/piix_pci.c
+++ b/hw/piix_pci.c
@@ -171,6 +171,23 @@ static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
     return 0;
 }
 
+static void i440fx_reset(void *opaque)
+{
+    PCII440FXState *d = opaque;
+    uint8_t *pci_conf = d->dev.config;
+
+    pci_conf[0x59] = 0x00; // Reset PAM setup
+    pci_conf[0x5a] = 0x00;
+    pci_conf[0x5b] = 0x00;
+    pci_conf[0x5c] = 0x00;
+    pci_conf[0x5d] = 0x00;
+    pci_conf[0x5e] = 0x00;
+    pci_conf[0x5f] = 0x00;
+    pci_conf[0x72] = 0x02; // And SMM
+
+    i440fx_update_memory_mappings(d);
+}
+
 static int i440fx_post_load(void *opaque, int version_id)
 {
     PCII440FXState *d = opaque;
@@ -217,6 +234,8 @@ static int i440fx_initfn(PCIDevice *dev)
     d->dev.config[I440FX_SMRAM] = 0x02;
 
     cpu_smm_register(&i440fx_set_smm, d);
+
+    qemu_register_reset(i440fx_reset, d);
     return 0;
 }
 

-- 
dwmw2
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