[SeaBIOS] [PATCH] Only perform SMP setup on QEMU.

[Kevin O'Connor]

The SMP setup initializes MTRRs on extra CPUs and populates the
CountCPUs variable.  On coreboot the CPUs should already be
initialized and the CountCPUs variable isn't used anywhere.

There have also been reports of the SIPI does not work on some real
machines.  So, it's best not to invoke one if it isn't needed.

Signed-off-by: Kevin O'Connor <kevin at koconnor.net>
---
 src/smp.c | 23 ++++++++++-------------
 1 file changed, 10 insertions(+), 13 deletions(-)

diff --git a/src/smp.c b/src/smp.c
index 1590d65..f971647 100644
--- a/src/smp.c
+++ b/src/smp.c
@@ -83,6 +83,9 @@ int apic_id_is_present(u8 apic_id)
 void
 smp_setup(void)
 {
+    if (!CONFIG_QEMU)
+        return;
+
     ASSERT32FLAT();
     u32 eax, ebx, ecx, cpuid_features;
     cpuid(1, &eax, &ebx, &ecx, &cpuid_features);
@@ -112,13 +115,11 @@ smp_setup(void)
     u32 val = readl(APIC_SVR);
     writel(APIC_SVR, val | APIC_ENABLED);
 
-    if (CONFIG_QEMU) {
-        /* Set LINT0 as Ext_INT, level triggered */
-        writel(APIC_LINT0, 0x8700);
+    /* Set LINT0 as Ext_INT, level triggered */
+    writel(APIC_LINT0, 0x8700);
 
-        /* Set LINT1 as NMI, level triggered */
-        writel(APIC_LINT1, 0x8400);
-    }
+    /* Set LINT1 as NMI, level triggered */
+    writel(APIC_LINT1, 0x8400);
 
     // broadcast SIPI
     barrier();
@@ -127,13 +128,9 @@ smp_setup(void)
     writel(APIC_ICR_LOW, 0x000C4600 | sipi_vector);
 
     // Wait for other CPUs to process the SIPI.
-    if (CONFIG_QEMU) {
-        u8 cmos_smp_count = inb_cmos(CMOS_BIOS_SMP_COUNT);
-        while (cmos_smp_count + 1 != readl(&CountCPUs))
-            yield();
-    } else {
-        msleep(10);
-    }
+    u8 cmos_smp_count = inb_cmos(CMOS_BIOS_SMP_COUNT);
+    while (cmos_smp_count + 1 != readl(&CountCPUs))
+        yield();
 
     // Restore memory.
     *(u64*)BUILD_AP_BOOT_ADDR = old;
-- 
1.7.11.7