[SeaBIOS] [PATCH v2 19/19] Add UmbStart, UmbEnd fields to EFI_COMPATIBILITY16_TABLE

[David Woodhouse]

From: David Woodhouse <David.Woodhouse at intel.com>

We need this proposed addition to the CSM spec, or OVMF will make the whole
region from 0xC0000 to 0xFFFFF read-only before invoking our Legacy16Boot
method. Read-only stack considered harmful.

http://www.sourceforge.net/mailarchive/forum.php?thread_name=50FD7290.9060003%40redhat.com&forum_name=edk2-devel

Signed-off-by: David Woodhouse <David.Woodhouse at intel.com>
---
 src/LegacyBios.h | 11 +++++++++++
 src/csm.c        |  2 ++
 2 files changed, 13 insertions(+)

diff --git a/src/LegacyBios.h b/src/LegacyBios.h
index 65ace3b..69eabd1 100644
--- a/src/LegacyBios.h
+++ b/src/LegacyBios.h
@@ -228,6 +228,17 @@ typedef struct {
   /// Maximum PCI bus number assigned.
   ///
   UINT8                             LastPciBus;
+
+  ///
+  /// Start address of UMB RAM (>> 12)
+  ///
+  UINT8                             UmbStart;
+
+  ///
+  /// End address of UMB RAM (>> 12)
+  ///
+  UINT8                             UmbEnd;
+
 } EFI_COMPATIBILITY16_TABLE;
 
 ///
diff --git a/src/csm.c b/src/csm.c
index c453ebd..352c3c2 100644
--- a/src/csm.c
+++ b/src/csm.c
@@ -28,6 +28,8 @@ EFI_COMPATIBILITY16_TABLE csm_compat_table VAR32FLATVISIBLE __aligned(16) = {
     .Compatibility16CallOffset = 0 /* Filled in by checkrom.py */,
     .OemIdStringPointer = (u32)"SeaBIOS",
     .AcpiRsdPtrPointer = (u32)&csm_rsdp,
+    .UmbStart = 0xe0,
+    .UmbEnd = 0xf0,
 };
 
 
-- 
1.8.1