[SeaBIOS] [PATCH] xhci: allocate scratch pad buffers
kevin at koconnor.net
Fri Dec 27 19:51:26 CET 2013
On Tue, Dec 24, 2013 at 02:09:17AM +0100, Idwer Vollering wrote:
> 2013/12/24 Kevin O'Connor <kevin at koconnor.net>:
> > On Sun, Dec 22, 2013 at 09:54:02PM -0500, Kevin O'Connor wrote:
> > FYI, it seems my USB3 controller really wants to see 64bit writes to
> > pci registers. With the change below (on top of the other changes) I
> > can now boot my e350m1 from a USB3 flash drive.
> > I'm still seeing failures on my keyboard/mouse though:
> This is captured on my f2a85-m, with CONFIG_DEBUG_LEVEL=7:
>From IRC, I understand that after you applied my last "status
direction" patch you were able to get your high speed flash device to
work on the xhci controller, but not your keyboard.
Can you also try the patch below? I still can't get any high/low
speed devices to work (though my super speed flash device does work).
Maybe you'll have more luck with this patch though.
Author: Kevin O'Connor <kevin at koconnor.net>
Date: Fri Dec 27 13:37:11 2013 -0500
xhci: Set the interval parameter on interrupt pipes.
Be sure to set the interval parameter when creating an interrupt based
Signed-off-by: Kevin O'Connor <kevin at koconnor.net>
diff --git a/src/hw/usb-xhci.c b/src/hw/usb-xhci.c
index d0df6ee..9d5449c 100644
@@ -895,6 +895,8 @@ xhci_alloc_pipe(struct usbdevice_s *usbdev
in->slot.ctx |= (31 << 27); // context entries
int e = pipe->epid-1;
+ if (eptype == USB_ENDPOINT_XFER_INT)
+ in->ep[e].ctx = (usb_getFrameExp(usbdev, epdesc) + 3) << 16;
in->ep[e].ctx |= (eptype << 3);
if (epdesc->bEndpointAddress & USB_DIR_IN)
in->ep[e].ctx |= (1 << 5);
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