[SeaBIOS] [PATCH] xhci: allocate scratch pad buffers

[Kevin O'Connor]

On Mon, Dec 23, 2013 at 06:55:41PM -0500, Kevin O'Connor wrote:
> On Sun, Dec 22, 2013 at 09:54:02PM -0500, Kevin O'Connor wrote:
> > On Fri, Dec 13, 2013 at 02:25:39PM -0500, Kevin O'Connor wrote:
> > > On Fri, Dec 13, 2013 at 01:27:45PM -0500, Kevin O'Connor wrote:
> > > > 01.342: xhci hcc=40050af hcs=4000440
> > > > 
> > > > I think this means that Context Size (CSZ) == 64 bytes and the
> > > > controller isn't compatible with the seabios driver?
> > > 
> > > FYI, with the (incredibly ugly) patch below, I get a little further.
> > 
> > FYI, with the (incredibly ugly) patch from the previous mail and with
> > a USB3 flash drive I seem to get slightly further.
> 
> FYI, it seems my USB3 controller really wants to see 64bit writes to
> pci registers.  With the change below (on top of the other changes) I
> can now boot my e350m1 from a USB3 flash drive.
> 
> I'm still seeing failures on my keyboard/mouse though:
> 
> 01.146: XHCI port #2: 0x00200a03, powered, enabled, pls 0, speed 2 [Low]
> 01.163: xhci_control: control xfer failed (cc 6)

Looks like the direction field of the status transmission is not
correct.  I can now get a little further with low speed devices, but
it's still failing.

01.134: /c7f9c000\ Start thread
01.134: |c7f9c000| xhci_hub_detect port #2: 0x000202e1, powered, pls 7, speed 0 [ - ]
01.136: |c7f9c000| xhci_hub_reset port #2: 0x000202e1, powered, pls 7, speed 0 [ - ]
01.136: |c7f9c000| XHCI port #2: 0x00200a03, powered, enabled, pls 0, speed 2 [Low]
01.136: |c7f9c000| set_address 0x000eda30
01.136: |c7f9c000| _malloc zone=0xc7fafed3 size=316 align=100 ret=0xc7fbf000 (detail=0xc7fa3460)
01.136: |c7f9c000| _malloc zone=0xc7fafed7 size=4180 align=40 ret=0x000eb000 (detail=0xc7fa3430)
01.136: |c7f9c000| xhci_alloc_pipe: usbdev 0xc7fa3580, ring 0xc7fbf000, slotid 0, epid 1
01.136: |c7f9c000| xhci_cmd_enable_slot:
01.136: |c7f9c000| xhci_trb_queue: ring 0xc7fbfc00 [nidx 4, len 0]
01.136: |c7f9c000| xhci_process_events: ring 0xc7fbf900 [trb 0xc7fbf980, evt 0xc7fbfa00, type 32, eidx 9, cc 1]
01.136: |c7f9c000| xhci_process_events: ring 0xc7fbfc00 [trb 0xc7fbfc30, evt 0xc7fbfd00, type 33, eidx 4, cc 1]
01.136: |c7f9c000| xhci_control: enable slot: got slotid 2
01.136: |c7f9c000| xhci_control: root port 2, route 0x0
01.136: |c7f9c000| xhci_cmd_address_device: slotid 2
01.136: |c7f9c000| xhci_trb_queue: ring 0xc7fbfc00 [nidx 5, len 0]
01.138: |c7f9c000| xhci_update_pipe: usbdev 0xc7fa3580, ring 0xc7fbf000, slotid 2, epid 1
01.138: |c7f9c000| config_usb: 0xc7fbf120
01.138: |c7f9c000| xhci_trb_queue: ring 0xc7fbf000 [nidx 1, len 8]
01.138: |c7f9c000| xhci_trb_queue: ring 0xc7fbf000 [nidx 2, len 8]
01.138: |c7f9c000| xhci_trb_queue: ring 0xc7fbf000 [nidx 3, len 0]
01.138: |c7f9c000| xhci_xfer_kick: ring 0xc7fbf000, slotid 2, epid 1
01.138: |c7f9c000| xhci_process_events: ring 0xc7fbfc00 [trb 0xc7fbfc50, evt 0xc7fbfd00, type 33, eidx 6, cc 17]
01.138: |c7f9c000| xhci_process_events: ring 0xc7fbf000 [trb 0xc7fbf020, evt 0xc7fbf100, type 32, eidx 3, cc 1]
01.138: |c7f9c000| device rev=0200 cls=00 sub=00 proto=00 size=08
01.138: |c7f9c000| xhci_update_pipe: usbdev 0xc7fa3580, ring 0xc7fbf000, slotid 2, epid 1
01.138: |c7f9c000| xhci_trb_queue: ring 0xc7fbf000 [nidx 4, len 8]
01.138: |c7f9c000| xhci_trb_queue: ring 0xc7fbf000 [nidx 5, len 9]
01.138: |c7f9c000| xhci_trb_queue: ring 0xc7fbf000 [nidx 6, len 0]
01.138: |c7f9c000| xhci_xfer_kick: ring 0xc7fbf000, slotid 2, epid 1
01.139: |c7f9c000| xhci_process_events: ring 0xc7fbfc00 [trb 0xc7fbfc70, evt 0xc7fbfd00, type 33, eidx 8, cc 1]
01.139: |c7f9c000| _malloc zone=0xc7fafec7 size=34 align=10 ret=0xc7fa3140 (detail=0xc7fa3350)
01.139: |c7f9c000| xhci_trb_queue: ring 0xc7fbf000 [nidx 7, len 8]
01.139: |c7f9c000| xhci_trb_queue: ring 0xc7fbf000 [nidx 8, len 34]
01.139: |c7f9c000| xhci_trb_queue: ring 0xc7fbf000 [nidx 9, len 0]
01.139: |c7f9c000| xhci_xfer_kick: ring 0xc7fbf000, slotid 2, epid 1
01.140: |c7f9c000| xhci_process_events: ring 0xc7fbf000 [trb 0xc7fbf080, evt 0xc7fbf100, type 32, eidx 9, cc 1]
01.140: |c7f9c000| xhci_trb_queue: ring 0xc7fbf000 [nidx 10, len 8]
01.140: |c7f9c000| xhci_trb_queue: ring 0xc7fbf000 [nidx 11, len 0]
01.140: |c7f9c000| xhci_xfer_kick: ring 0xc7fbf000, slotid 2, epid 1
01.141: |c7f9c000| xhci_process_events: ring 0xc7fbf000 [trb 0xc7fbf0a0, evt 0xc7fbf100, type 32, eidx 11, cc 1]
01.141: |c7f9c000| usb_hid_setup 0xc7fbf120
01.141: |c7f9c000| xhci_trb_queue: ring 0xc7fbf000 [nidx 12, len 8]
01.141: |c7f9c000| xhci_trb_queue: ring 0xc7fbf000 [nidx 13, len 0]
01.141: |c7f9c000| xhci_xfer_kick: ring 0xc7fbf000, slotid 2, epid 1
01.142: |c7f9c000| xhci_process_events: ring 0xc7fbf000 [trb 0xc7fbf0c0, evt 0xc7fbf100, type 32, eidx 13, cc 1]
01.141: |c7f9c000| _malloc zone=0xc7fafed7 size=316 align=100 ret=0x000eae00 (detail=0xc7fa3790)
01.141: |c7f9c000| _malloc zone=0xc7fafed7 size=4 align=10 ret=0x000eda20 (detail=0xc7fa3760)
01.142: |c7f9c000| xhci_alloc_pipe: usbdev 0xc7fa3580, ring 0x000eae00, slotid 2, epid 3
01.141: |c7f9c000| binterval=10 s0=f8200000 s1=00020000 e0=00000000 e1=00040038
01.141: |c7f9c000| xhci_cmd_configure_endpoint: slotid 2, add 0x9, del 0x0
01.141: |c7f9c000| xhci_trb_queue: ring 0xc7fbfc00 [nidx 9, len 0]
01.142: |c7f9c000| xhci_process_events: ring 0xc7fbfc00 [trb 0xc7fbfc80, evt 0xc7fbfd00, type 33, eidx 9, cc 17]
01.142: |c7f9c000| xhci_alloc_pipe: configure endpoint: failed (cc 17)
01.142: |c7f9c000| _free 0x000eae00 (detail=0xc7fa3790)
01.142: |c7f9c000| _free 0xc7fa3140 (detail=0xc7fa3350)
01.142: |c7f9c000| xhci_cmd_disable_slot: slotid 2
01.142: |c7f9c000| xhci_trb_queue: ring 0xc7fbfc00 [nidx 10, len 0]
01.143: |c7f9c000| xhci_process_events: ring 0xc7fbfc00 [trb 0xc7fbfc90, evt 0xc7fbfd00, type 33, eidx 10, cc 1]
01.143: |c7f9c000| _free 0xc7fa3580 (detail=0xc7fa35a0)
01.143: \c7f9c000/ End thread

-Kevin


--- a/src/hw/usb-xhci.c
+++ b/src/hw/usb-xhci.c
@@ -379,6 +379,7 @@ static void xhci_process_events(struct usb_xhci_s *xhci)
         u32 addr = (u32)(&ir->erdp_low);
         u32 erdp = (u32)(evts->ring + nidx);
         pci_writel(addr, erdp);
+        pci_writel((u32)(&ir->erdp_high), 0);
     }
 }
 
@@ -620,7 +621,7 @@ static void xhci_xfer_data(struct xhci_pipe *pipe,
     xhci_xfer_queue(pipe, &trb);
 }
 
-static void xhci_xfer_status(struct xhci_pipe *pipe, int dir)
+static void xhci_xfer_status(struct xhci_pipe *pipe, int dir, int datalen)
 {
     ASSERT32FLAT();
     struct xhci_trb trb;
@@ -628,7 +629,7 @@ static void xhci_xfer_status(struct xhci_pipe *pipe, int dir)
     memset(&trb, 0, sizeof(trb));
     trb.control  |= (TR_STATUS << 10); // trb type
     trb.control  |= TRB_TR_IOC;
-    if (dir)
+    if (!datalen || !dir)
         trb.control |= (1 << 16);
 
     xhci_xfer_queue(pipe, &trb);
@@ -903,6 +904,10 @@ xhci_alloc_pipe(struct usbdevice_s *usbdev
         in->ep[e].deq_high = 0;
         in->ep[e].length   = pipe->pipe.maxpacket;
 
+        dprintf(1, "binterval=%d s0=%08x s1=%08x e0=%08x e1=%08x\n"
+                , epdesc->bInterval, in->slot.ctx[0], in->slot.ctx[1]
+                , in->ep[e].ctx[0], in->ep[e].ctx[1]);
+
         int cc = xhci_cmd_configure_endpoint(pipe->dev);
         if (cc != CC_SUCCESS) {
             dprintf(1, "%s: configure endpoint: failed (cc %d)\n", __func__, cc);
@@ -1006,7 +1011,7 @@ xhci_control(struct usb_pipe *p, int dir, const void *cmd, int cmdsize
     xhci_xfer_setup(pipe, req, dir, datalen);
     if (datalen)
         xhci_xfer_data(pipe, dir, data, datalen);
-    xhci_xfer_status(pipe, dir);
+    xhci_xfer_status(pipe, dir, datalen);
 
     cc = xhci_event_wait(xhci, &pipe->reqs, 1000);
     if (cc != CC_SUCCESS) {