[SeaBIOS] [PATCH 4/3] Broken attempt to add Oxford Semi PCI serial port support

[David Woodhouse]

Based on
http://git.chromium.org/gitweb/?p=chromiumos/third_party/seabios.git;a=commitdiff;h=9b39499125f22627aaedaaaadabfde787c50d51c;hp=dd16541f6b1df12b1431fa3c34ef875f0d99c0f1

Doesn't work:
ERROR: .data.varinit./home/dwmw2/git/seabios/src/hw/pci.c.93 is VARVERIFY32INIT but used from ['.text.runtime./home/dwmw2/git/seabios/src/resume.c.149', '.text.__callrom', '.text.serial_debug_preinit', '.text.pci_find_device']
make: *** [out/romlayout16.lds] Error 1

It might also need to re-discover its serial ports after PCI enumeration
and BAR assignment. It may be set up at a fixed location for early
debug, then moved when PCI is set up for real.

Perhaps the Oxford code needs to run something once, early, which just
discovers which PCI B/D/F to use, and then looks a lot more like the
Quark code in find_mmio_serial().

Signed-off-by-but-do-not-use-as-is: David Woodhouse <David.Woodhouse at intel.com>
---
 src/Kconfig       |  7 +++++++
 src/hw/serialio.c | 15 ++++++++++++++-
 2 files changed, 21 insertions(+), 1 deletion(-)

diff --git a/src/Kconfig b/src/Kconfig
index 696ab46..a0ef46a 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -490,6 +490,13 @@ menu "Debugging"
         default n
         help
             Use Quark UART1 (PCI device 0x14, function 5) for serial debug.
+    config DEBUG_SERIAL_OXFORD
+        bool "OXPCIe 952 serial port debugging"
+        depends on DEBUG_SERIAL
+	select DEBUG_SERIAL_MMIO
+        default n
+        help
+            Send debugging information to Oxford Semiconductors PCI serial port.
     config DEBUG_SERIAL_PORT
         depends on DEBUG_SERIAL && !DEBUG_SERIAL_MMIO
         hex "Serial port base address"
diff --git a/src/hw/serialio.c b/src/hw/serialio.c
index b2bc68f..3310c7f 100644
--- a/src/hw/serialio.c
+++ b/src/hw/serialio.c
@@ -53,7 +53,20 @@ find_mmio_serial(void)
             return 0;
         }
     }
-
+    if (CONFIG_DEBUG_SERIAL_OXFORD) {
+        struct pci_device *oxpcie_dev;
+        // Detect Startech MPEX1S952
+        oxpcie_dev = pci_find_device(0x1415, 0xc158);
+        if (!oxpcie_dev) // Startech PEX1S1PMINI
+            oxpcie_dev = pci_find_device(0x1415, 0xc11b);
+        if (oxpcie_dev) {
+            u32 bar = pci_config_readl(oxpcie_dev->bdf, PCI_BASE_ADDRESS_0);
+            if (!(bar & 0xf)) {
+                set_serial_addr(bar, 1);
+                return 0;
+            }
+        }
+    }
     return -1;
 }
 
-- 
1.8.3.1


-- 
David Woodhouse                            Open Source Technology Centre
David.Woodhouse at intel.com                              Intel Corporation
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