[SeaBIOS] [PATCH] Update EFI_COMPATIBILITY16_TABLE to match 0.98 spec update

[David Woodhouse]

We expect to use the space between the top of option ROMs and the bottom
of our own BIOS code as a stack. OVMF was previously marking the whole
region from 0xC0000 to 0xFFFFF read-only before invoking our Legacy16Boot
method. Read-only stack considered harmful.

Version 0.98 of the CSM spec adds the UmaAddress and UmaSize fields, which
allow the CSM to specify a memory region that needs to be writable.

Signed-off-by: David Woodhouse <David.Woodhouse at intel.com>
---
The corresponding patch hasn't hit the OVMF/EDKII tree yet, but that
shouldn't stop us from applying it anyway. CSM support was completely
broken before this anyway — it required *some* way of hacking around
this problem. And this patch does not harm on its own either.

 src/fw/csm.c         |  6 +++++-
 src/std/LegacyBios.h | 20 ++++++++++++++++++++
 2 files changed, 25 insertions(+), 1 deletion(-)

diff --git a/src/fw/csm.c b/src/fw/csm.c
index afd7ffe..6fe3a1b 100644
--- a/src/fw/csm.c
+++ b/src/fw/csm.c
@@ -34,6 +34,8 @@ EFI_COMPATIBILITY16_TABLE csm_compat_table VARFSEG __aligned(16) = {
     .Compatibility16CallOffset = 0 /* Filled in by checkrom.py */,
     .OemIdStringPointer = (u32)"SeaBIOS",
     .AcpiRsdPtrPointer = (u32)&csm_rsdp,
+    .UmaAddress = 0xe0000,
+    .UmaSize = 0x10000,
 };
 
 EFI_TO_COMPATIBILITY16_INIT_TABLE *csm_init_table;
@@ -46,9 +48,11 @@ extern void __csm_return(struct bregs *regs) __noreturn;
 static void
 csm_return(struct bregs *regs)
 {
-    dprintf(3, "handle_csm returning AX=%04x\n", regs->ax);
+    u32 top = rom_get_max();
 
     PICMask = pic_irqmask_read();
+    csm_compat_table.UmaAddress = top;
+    csm_compat_table.UmaSize = 0xf0000 - top;
     __csm_return(regs);
 }
 
diff --git a/src/std/LegacyBios.h b/src/std/LegacyBios.h
index cf0c3c5..5170c37 100644
--- a/src/std/LegacyBios.h
+++ b/src/std/LegacyBios.h
@@ -228,6 +228,26 @@ typedef struct {
   /// Maximum PCI bus number assigned.
   ///
   UINT8                             LastPciBus;
+
+  ///
+  /// Start address of UMB RAM
+  ///
+  UINT32                            UmaAddress;
+
+  ///
+  /// Size of UMB RAM
+  ///
+  UINT32                            UmaSize;
+
+  ///
+  /// Start address of persistent allocation in high (>1MiB) memory
+  ///
+  UINT32                            HiPermanentMemoryAddress;
+
+  ///
+  /// Size of persistent allocation in high (>1MiB) memory
+  ///
+  UINT32                            HiPermanentMemorySize;
 } EFI_COMPATIBILITY16_TABLE;
 
 ///
-- 
1.8.3.1


-- 
David Woodhouse                            Open Source Technology Centre
David.Woodhouse at intel.com                              Intel Corporation
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