[SeaBIOS] [PATCH v3 0/8] q35 seabios support

[Jason Baron]

Hi,

Seabios bits for q35 support, I'm posting the qemu changes separately. The
patches require '-M pc_q35' and -L 'seabios dir with q35 changes' on the
qemu command line. Hopefully, we can make it the default for x86 at some future
point when we feel comfortable with it.

The current patches have been tested with basic install testing and memory testing
on f16, f17, windows 7 and windows 8. They can be run on the various BSD flavors
by adding a 'piix4-ide' device to the pci bus. ie: -device piix4-ide. Patches
have also been reported to work with a small dsdt change on OSX 10.6 as well.

I've dropped the ahci migration bits, which means q35 is not migratable at the
moment. I simply haven't had time to make them more complete yet.

I'm hoping that we'll come to some agreement on the minimal functionality
required for q35 to be merged.

Git trees:

git://github.com/jibaron/q35-qemu.git
git://github.com/jibaron/q35-seabios.git

Notes:

I've dropped automatic load of the dsdt table on the piix for now. We can't
pull this in until we have snapshot of the dsdt aml, and I wanted it to be
done at a clean seabios freeze point (Although I guess that could be the
current snapshot). I don't see the harm in pulling this in later though.

I've also gone to a model of the pci host being sparse:

00:00.0 Host bridge: Intel Corporation 82G33/G31/P35/P31 Express DRAM Controller
00:01.0 VGA compatible controller: Cirrus Logic GD 5446
00:02.0 Ethernet controller: Intel Corporation 82540EM Gigabit Ethernet Controller (rev 03)
00:1f.0 ISA bridge: Intel Corporation 82801IB (ICH9) LPC Interface Controller (rev 02)
00:1f.2 SATA controller: Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6 port SATA AHCI Controller (rev 02)
00:1f.3 SMBus: Intel Corporation 82801I (ICH9 Family) SMBus Controller (rev 02)

The idea is only to populate the essential stuff at 1f, and have the rest
filled out via command line options. In this way we have minimal bus configuration
with 1 slot occupied as in piix. Should make things easier for libvirt. And this
way user has complete control over things. For example, I have added support that
when '-usb' is passed the usb controllers for ich9 are filled out.

Todo:

-add ahci migration back (need to cover more fields, but basically works)
-add base addr for hpet in LPC device (for osx per agraf)
-convert hotplug to use MemoryRegionPortio for hotplug (need an IsaDevice?)

Thanks,

-Jason

Changes from v2:
 -Patch restructure (broke out ich9 chips + data structures separately)
 -added passthrough support
 -add support for -usb to fill out host pci bus
 -Dropped automatic load of dsdt table for piix
 -cleanups
 -dropped wmask on smbus (mst)
 -sparse host bus

Changes from v1:
 -Updated end of low mem from 0xe0000000 -> 0xb0000000 (Gerd Hoffmann)
        -so 0xb000000-0xc000000 is memconfig
        -0xc000000-0xfec00000 is 32-bit pci window
 -style/various cleanups
 -introduced IF_AHCI
 -introduced mach_if
 -split dsdt out of bios, now passed for piix4 as well (Paolo, Gerd)
 -Removed add opaque argument to pci_map_irq_fn (Michael S. Tsirkin)
 -removed patches that were merged in v1

Isaku Yamahata (5):
  seabios: acpi: add mcfg table.
  seabios: acpi, fadt: make while fadt initialization chipset specific
  seabios: pci: enable SERR of normal device.
  seabios: add q35 initialization functions.
  seabios: q35: add dsdt

Jan Kiszka (1):
  seabios: q35: Register PCI IRQs as active high in APIC mode

Jason Baron (2):
  seabios: make mttr UC area setup dynamic
  seabios: q35: add basic hotplug support

 Makefile              |    2 +-
 src/acpi.c            |  176 ++++++++-
 src/acpi.h            |   17 +
 src/config.h          |    1 -
 src/dev-q35.h         |   46 +++
 src/mtrr.c            |    5 +-
 src/pci.h             |    1 +
 src/pciinit.c         |   87 +++++-
 src/post.c            |    6 +-
 src/q35-acpi-dsdt.dsl |  980 +++++++++++++++++++++++++++++++++++++++++++++++++
 src/shadow.c          |   13 +
 src/smm.c             |   37 ++
 12 files changed, 1344 insertions(+), 27 deletions(-)
 create mode 100644 src/dev-q35.h
 create mode 100644 src/q35-acpi-dsdt.dsl