[SeaBIOS] [PATCH 17/20] acpi: rework enable bits
Gerd Hoffmann
kraxel at redhat.com
Wed Nov 28 10:17:46 CET 2012
Model the device enable bits as fields so they can be accessed
directly by name.
Signed-off-by: Gerd Hoffmann <kraxel at redhat.com>
---
src/acpi-dsdt.dsl | 49 ++++++++++++++++++++++++++++---------------------
1 files changed, 28 insertions(+), 21 deletions(-)
diff --git a/src/acpi-dsdt.dsl b/src/acpi-dsdt.dsl
index 947bcff..6ee3c8e 100644
--- a/src/acpi-dsdt.dsl
+++ b/src/acpi-dsdt.dsl
@@ -161,6 +161,21 @@ DefinitionBlock (
****************************************************************/
Scope(\_SB.PCI0.ISA) {
+
+ /* enable bits */
+ Field (\_SB.PCI0.PX13.P13C, AnyAcc, NoLock, Preserve)
+ {
+ Offset(0x5f),
+ , 7,
+ LPEN, 1, // LPT
+ Offset(0x67),
+ , 3,
+ CAEN, 1, // COM1
+ , 3,
+ CBEN, 1, // COM2
+ }
+ Name (FDEN, 1)
+
/* Real-time clock */
Device (RTC)
{
@@ -230,7 +245,15 @@ DefinitionBlock (
Name (_HID, EisaId ("PNP0700"))
Method (_STA, 0, NotSerialized)
{
- Return (0x0F)
+ Store (FDEN, Local0)
+ If (LEqual (Local0, 0))
+ {
+ Return (0x00)
+ }
+ Else
+ {
+ Return (0x0F)
+ }
}
Method (_CRS, 0, NotSerialized)
{
@@ -251,8 +274,7 @@ DefinitionBlock (
Name (_HID, EisaId ("PNP0400"))
Method (_STA, 0, NotSerialized)
{
- Store (\_SB.PCI0.PX13.DRSA, Local0)
- And (Local0, 0x80000000, Local0)
+ Store (LPEN, Local0)
If (LEqual (Local0, 0))
{
Return (0x00)
@@ -280,8 +302,7 @@ DefinitionBlock (
Name (_UID, 0x01)
Method (_STA, 0, NotSerialized)
{
- Store (\_SB.PCI0.PX13.DRSC, Local0)
- And (Local0, 0x08000000, Local0)
+ Store (CAEN, Local0)
If (LEqual (Local0, 0))
{
Return (0x00)
@@ -308,8 +329,7 @@ DefinitionBlock (
Name (_UID, 0x02)
Method (_STA, 0, NotSerialized)
{
- Store (\_SB.PCI0.PX13.DRSC, Local0)
- And (Local0, 0x80000000, Local0)
+ Store (CBEN, Local0)
If (LEqual (Local0, 0))
{
Return (0x00)
@@ -339,20 +359,7 @@ DefinitionBlock (
Scope(\_SB.PCI0) {
Device (PX13) {
Name (_ADR, 0x00010003)
-
- OperationRegion (P13C, PCI_Config, 0x5c, 0x24)
- Field (P13C, DWordAcc, NoLock, Preserve)
- {
- DRSA, 32,
- DRSB, 32,
- DRSC, 32,
- DRSE, 32,
- DRSF, 32,
- DRSG, 32,
- DRSH, 32,
- DRSI, 32,
- DRSJ, 32
- }
+ OperationRegion (P13C, PCI_Config, 0x00, 0xff)
}
}
--
1.7.1
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