[SeaBIOS] [PATCH 07/20] seabios: q35: add dsdt

[Jason Baron]

On Tue, Nov 27, 2012 at 10:20:58AM +0100, Gerd Hoffmann wrote:
> From: Isaku Yamahata <yamahata at valinux.co.jp>
> 
> add dsdt for q35 chipset of qemu.
> 

...

> +
> +    /* PCI express root port */
> +#define pcie_root_port(id, dev, fn)	\
> +    Scope (\_SB.PCI0) {                 \
> +        Device (PRP##id) {              \
> +            Name (_ADR, 0x##dev##fn)	\
> +         }                              \
> +    }
> +    pcie_root_port(0,  4, 0000)
> +    pcie_root_port(1, 18, 0000)
> +    pcie_root_port(2, 18, 0001)
> +    pcie_root_port(3, 18, 0002)
> +    pcie_root_port(4, 18, 0003)
> +    pcie_root_port(5, 18, 0004)
> +    pcie_root_port(6, 18, 0005)
> +
> +    Scope (\_SB.PCI0) {
> +        Device (PRP7) {
> +            Name (_ADR, 0x00190000)
> +         }
> +    }
> +
> +    /* PCI express upstream port */
> +#define pcie_downstream_port(dev)	\
> +    Device (PDP##dev) {                 \
> +        Name (_ADR, 0x##dev##0000)      \
> +    }
> +
> +#define pcie_upstream_port(fn)		\
> +    Scope (\_SB.PCI0.PRP7) {            \
> +        Device (PUP##fn) {              \
> +            Name (_ADR, 0x##0000##fn)	\
> +            pcie_downstream_port(0)     \
> +            pcie_downstream_port(1)     \
> +            pcie_downstream_port(2)     \
> +            pcie_downstream_port(3)     \
> +            pcie_downstream_port(4)     \
> +            pcie_downstream_port(5)     \
> +            pcie_downstream_port(6)     \
> +            pcie_downstream_port(7)     \
> +            pcie_downstream_port(8)     \
> +            pcie_downstream_port(9)     \
> +            pcie_downstream_port(a)     \
> +            pcie_downstream_port(b)     \
> +            pcie_downstream_port(c)     \
> +            pcie_downstream_port(d)     \
> +            pcie_downstream_port(e)     \
> +            pcie_downstream_port(f)     \
> +        }				\
> +    }
> +    pcie_upstream_port(0)
> +    pcie_upstream_port(1)
> +    pcie_upstream_port(2)
> +    pcie_upstream_port(3)
> +    pcie_upstream_port(4)
> +    pcie_upstream_port(5)
> +    pcie_upstream_port(6)
> +    pcie_upstream_port(7)
> +
> +
> +    /* PCI to PCI Bridge on bus 0*/
> +    Scope (\_SB.PCI0) {
> +        Device (PCI9) {
> +            Name (_ADR, 0x1e0000)       /* 0:1e.00 */
> +            Name (_UID, 9)
> +        }
> +    }
> +
> +#define pci_bridge(id, dev, uid)	\
> +    Scope (\_SB.PCI0.PCI9) {            \
> +        Device (PCI##id) {              \
> +            Name (_ADR, 0x##dev##0000)  \
> +            Name (_UID, uid)            \
> +        }                               \
> +    }
> +    pci_bridge(0, 1c, 5)
> +    pci_bridge(1, 1d, 6)
> +    pci_bridge(2, 1e, 7)
> +    pci_bridge(3, 1f, 8)
> +

I think we should drop this entire pcie root port/bridge sections, at
least for now. These were here from when qemu was creating a default set
of bridges and pcie root ports. Now that we've gone to a model where we
have a minimal set of default devices, this doesn't match what qemu is
doing. We might need to re-visit this at a later point, but I think we
should drop it for now.

Thanks,

-Jason