[SeaBIOS] Issues on initialization of PCI devices below root.

lautriv lautriv at coldplug.net
Fri Nov 23 22:06:01 CET 2012

On 11/23/2012 08:56 AM, Kevin O'Connor wrote:
> On Thu, Nov 22, 2012 at 12:45:57PM +0100, lautriv wrote:
>> On 11/21/2012 07:11 PM, Stefan Reinauer wrote:
>>> * lautriv<lautriv at coldplug.net>   [121121 13:35]:
>>>> Hello,
>>>> i tried to get seabios up via payload from coreboot and failed on
>>>> the initialisation
>>>> of neccessary devices.
>>>> The board in Question is a Tyan S4882, consisting of K8 northbridge,
>>>> 8131 southbridge, 8111 southbridge and Winbond w83627hf SuperIO.
>>>> You will see on the following pastebin-url that coreboot does a
>>>> proper init and can see all relevant devices.
>>>> I was also able to get VGA up via coreboot ( to reflect an
>>>> accessible device below root ) but not from within seabios. It
>>>> probes only against PCI 00:18.0 ... 00:18.3 which are on the
>>>> northbridge itself.
>>>> I had a look on the sources and found it should see and init the
>>>> whole tree, also checked my sources against some patches i found on
>>>> the net and they are all applied or superseded.
>>> I think you need to change the board's HT configuration so that the
>>> southbridge ends up on bus 0 instead of 1 (with no pci bridge pointing
>>> to bus 1)
>> ok, i investigated a few hours on the coreboot part of
>> hardware-init, device-tree and surrounding stuff.
>> where i found coreboot itself can always find and init devices while
>> seabios fails right after the northbridge, mentioning "MaxPCIBus 00"
>> which was always a miracle to me.
>> however, after the init was already working, and i could not see a
>> problem on the fly, i took a crossbar and changed one line in pci.h
>> from "extern int MaxPCIBus;" to "extern int MaxPCIBus = 5;". this is
>> no solution or even gentlemen like but overrides the tree-building
>> loops with success.
>> finally i got this -->  http://pastebin.com/iqQJ1m7C
>> not perfect and needs more tuning but shows clearly something in the
>> routines of PCI initialisation returns too early in the process.
> One can get the same effect by modifying the extra-pci-roots variable
> as described at:
> http://www.coreboot.org/SeaBIOS#Other_Configuration_items
> This variable can be used to tell SeaBIOS about multiple independent
> pci root buses.
> However, in previous communications it was indicated that your board
> does not have extra root buses, but instead has standard PCI bridges.
> If this is the case, then the bridges are not being configured
> properly in coreboot, as SeaBIOS will find and probe standard PCI
> bridges when they are configured properly.
> -Kevin
Thanks for all replies, the problem is solved.
I have to apologise my limited view on the whole while i was in hurry 
and finally blamed seabios for something where it not failed.

The very first attempt of all, even before i registered at this list was 
to add etc/extra-pci-roots.
For some reason, that failed. so i checked the debugging output and 
found seabios doesn't never look behind the northbridge's LDT0 where 
coreboot already saw the rest of the devices and was also able to init 
All attempts to change SB_HT_CHAIN_ON_BUS0, HT_CHAIN_UNITID_BASE and 
HT_CHAIN_END_UNITID_BASE and different changes in the devicetree.cb were 
leading in the same edge, never got seabios to start at LDT1 ( using the 
right chain as the correct root ).

My conclusion was it must be within seabios and the forced 
initialisation supported that opinion because it was successful.
next step was to get a clue about pci.c, i inserted additional lines to 
output runtime-values of each step,
found that LDT1 was handled afterwards as independent bus ( what it in 
fact is ) got more and more the impression that code __should__ do the 
trick but won't.

Finally, i removed all binaries and presets, did the whole thing once 
again from scratch and this time
my ./cbfstool coreboot.rom add -n etc/extra-pci-roots blah blah had the 
desired effect.

i may mention, the very first flash of coreboot gave me a big empty 
space between coreboot_ram and the payload of seabios (around 40 k 
unused) while the working version is aligned on boundary. so maybe the 
extra-pci-roots were not seen because of unusual issues on the flash. ( 
happend only the first time )

Thanks again for all suggestions, maybe i come back while tweaking this 
box now ;)

Regards Helmut

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