[SeaBIOS] [PATCH v2 3/4] uq/master: Add CPU eject handling for acpi_piix4

[Vasilis Liaskovitis]

Add stub functions for CPU eject callback. Define cpu_acpi_eject property and
enable eject callback only for pc-1.1 machine model.

Signed-off-by: Vasilis Liaskovitis <vasilis.liaskovitis at profitbricks.com>
---
 hw/acpi_piix4.c |   20 ++++++++++++++++++++
 hw/pc_piix.c    |    8 ++++++++
 2 files changed, 28 insertions(+), 0 deletions(-)

diff --git a/hw/acpi_piix4.c b/hw/acpi_piix4.c
index 96e1ce8..8475aa6 100644
--- a/hw/acpi_piix4.c
+++ b/hw/acpi_piix4.c
@@ -40,6 +40,7 @@
 
 #define GPE_BASE 0xafe0
 #define PROC_BASE 0xaf00
+#define PROC_EJ_BASE 0xaf20
 #define GPE_LEN 4
 #define PCI_BASE 0xae00
 #define PCI_EJ_BASE 0xae08
@@ -80,6 +81,8 @@ typedef struct PIIX4PMState {
     struct gpe_regs gpe_cpu;
     struct pci_status pci0_status;
     uint32_t pci0_hotplug_enable;
+    /* for cpu hotplug */
+    uint32_t cpu_acpi_eject;
 } PIIX4PMState;
 
 static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s);
@@ -424,6 +427,7 @@ static PCIDeviceInfo piix4_pm_info = {
     .class_id           = PCI_CLASS_BRIDGE_OTHER,
     .qdev.props         = (Property[]) {
         DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
+        DEFINE_PROP_UINT32("cpu_acpi_eject", PIIX4PMState, cpu_acpi_eject, 0),
         DEFINE_PROP_END_OF_LIST(),
     }
 };
@@ -497,6 +501,17 @@ static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val)
     PIIX4_DPRINTF("pcihotplug write %x <== %d\n", addr, val);
 }
 
+static uint32_t cpuej_read(void *opaque, uint32_t addr)
+{
+    PIIX4_DPRINTF("cpuej read %x\n", addr);
+    return 0;
+}
+
+static void cpuej_write(void *opaque, uint32_t addr, uint32_t val)
+{
+    PIIX4_DPRINTF("cpuej write %x <== %d\n", addr, val);
+}
+
 static uint32_t pciej_read(void *opaque, uint32_t addr)
 {
     PIIX4_DPRINTF("pciej read %x\n", addr);
@@ -555,6 +570,11 @@ static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s)
     register_ioport_write(PROC_BASE, 32, 1, gpe_writeb, s);
     register_ioport_read(PROC_BASE, 32, 1,  gpe_readb, s);
 
+    if (s->cpu_acpi_eject) {
+        register_ioport_write(PROC_EJ_BASE, 32, 1, cpuej_write, s);
+        register_ioport_read(PROC_EJ_BASE, 32, 1,  cpuej_read, s);
+    }
+
     register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, pci0_status);
     register_ioport_read(PCI_BASE, 8, 4,  pcihotplug_read, pci0_status);
 
diff --git a/hw/pc_piix.c b/hw/pc_piix.c
index ac251c6..6d61567 100644
--- a/hw/pc_piix.c
+++ b/hw/pc_piix.c
@@ -380,6 +380,14 @@ static QEMUMachine pc_machine_v1_1 = {
     .desc = "Standard PC",
     .init = pc_init_pci,
     .max_cpus = 255,
+    .compat_props = (GlobalProperty[]) {
+        {
+            .driver   = "PIIX4_PM",
+            .property = "cpu_acpi_eject",
+            .value    = stringify(1),
+        },
+        { /* end of list */ }
+    },
 };
 
 static QEMUMachine pc_machine_v1_0 = {
-- 
1.7.7.3