[SeaBIOS] synching GPE0_BLK between OVMF and qemu

[Laszlo Ersek]

On 04/27/12 17:12, Jordan Justen wrote:
> On Fri, Apr 27, 2012 at 07:31, Laszlo Ersek <lersek at redhat.com> wrote:

>> edk2's "OvmfPkg/AcpiTables/Platform.h" specifies GPE0_BLK at 0x40C,
>> while qemu's "hw/acpi_piix4.c" expects the guest to access it at 0xAFE0.
>> Which macro should be modified to get them in sync?
> 
> Do they need to be in sync?

It appears to me so:

https://bugzilla.redhat.com/show_bug.cgi?id=653382#c22

> We set PBMA to 0x400 in OvmfPkg/Library/AcpiTimerLib/AcpiTimerLib.c,
> so isn't 0x40c correct?

Considering OVMF in isolation, I presume it's self-consistent.

However, is it necessary (a) to group these ACPI registers closely
together, (b) to base the "group" at 0x400?

>From "5.2.9 Fixed ACPI Description Table (FADT)" in the ACPI spec (v5.0)
it would appear OVMF can freely choose where to put GPE0_BLK, in both
senses (ie. port address considered alone, and also in relation to the
other ACPI registers).

Considering SeaBIOS again (build_fadt()):
- PORT_ACPI_PM_BASE is 0xb000,
- PM1a_EVT_BLK, PM1a_CNT_BLK and PM_TMR_BLK are located consecutively
from this base,
- but GPE0_BLK is placed at 0xafe0 (build_fadt() -->
pci_init_device(fadt_init_tbl) --> piix4_fadt_init())

But I'm likely missing something ^W everything...

Thanks!
Laszlo