[SeaBIOS] seabios: About the reset mem address

[Kevin O'Connor]

On Wed, Sep 28, 2011 at 12:54:27PM -0400, Amos Kong wrote:
> Hi all,
> 
> http://www.coreboot.org/Developer_Manual
> Hardware Reset(From Intel's "64 and IA-32 Architectures Software Developer’s Manual" (doc 253668-021 October 2006), Volume 3A, Section 9.1.4:)
> 
[...]
>  [CS base address = CS segment selector * 16]

"CS base address" will be assigned "CS segment selector * 16" when far
jumping in 16bit real mode.  However, on reset the "CS base address"
is set to 0xFFFF0000.

> ==> Why the reset mem addresses are different? Which one is correct?

They are both correct - the execution address is always CS_base +
%eip, and CS_base is set to %cs * 16 when far jumping - however, the
machine starts with CS_base set to a value that one couldn't normally
obtain by far jumping.

> Other Questions:
> 1. which point does the BIOS start from? reset_vector? transition32? entry_elf?

On QEmu, SeaBIOS starts at 0xfffffff0, which is an alias to
reset_vector (QEmu maps the bios to both 0xffff0000 and 0xf0000).
reset_vector far jumps to entry_post (f000:e05b), which then calls
transition32 to go into 32bit mode and invoke handle_post.

On Coreboot, coreboot is called at system start (0xfffffff0) - it does
a whole bunch of system initialization and then uncompresses seabios
to 0xf0000 and jumps to entry_elf, which then calls handle_post.

> 2. If I only compile seabios, and load the bios.bin to qemu, coreboot will not be used?

Correct.

> what's the relationship between coreboot and seabios ?

Coreboot does very early hardware initialization (eg, initializing
memory controller).  SeaBIOS implements a 16bit legacy BIOS.  SeaBIOS
is usable by both coreboot and QEmu (and other emulators).

-Kevin