[SeaBIOS] non-emulated AHCI hardware
scott at notabs.org
Thu May 26 20:09:50 CEST 2011
Gerd Hoffmann wrote:
]> Attached is a two part version of the previous patch. Stage1 is enough
]> to get through most OS installs. Stage2 adds unaligned buffer support
]> needed for MS-DOS.
]Hmm, patch #1 is still a collection of multiple changes, looks a bit
]like trying this and that until it somehow worked, without figuring
]which changes where needed to make the box boot.
Thank you for the feedback. This is a pretty harsh assessment of work
that transforms non-functioning code into something usable on real hardware.
Have you ever written code for real hardware or do work strictly with
] Also the changelog
]should describe what was changed and why, not only the effect of the
These documents will help you understand the changes:
]Polling the IRQ status looks like a sensible thing to do. Note that
]there might be multiple bits set in the IRQ status register, so you
]can't use irqbits == 0x01 to check the status. qemu fails to boot
]because of that bug.
Have you considered the possibility that the reason this works on real
hardware and not qemu is that the qemu AHCI model has an erratum?
] Also it isn't obvious why you are looking for
]others than the "Device to Host Register FIS" interrupt. Care to explain?
I don't understand this question.
]I've attached a patch which switches ahci over to irq status polling,
]based on your patch. Works nicely in qemu. Can you give it a spin on
It fails on real (AMD) hardware.
I am surprised by qemu bias of your questions. The type of question I
expected is "great to hear it works on AMD hardware, but what about Intel
hardware?" My answer would be that I cannot easily test the code on Intel
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