[SeaBIOS] [PATCH v2] Make pci memory window configurable.

Gerd Hoffmann kraxel at redhat.com
Wed May 4 10:10:10 CEST 2011


> I don't know of any alignment restrictions other than that specified
> in the BAR.  SeaBIOS doesn't setup MTRRs right now for pref mem.


> Looks like each bus uses 1meg alignment for all devices on that bus.

That looks like a random pick to me.  Isaku?  Looking at all devices 
behind the bridge, then pick something where all bars fit in and are 
properly aligned should work, right?


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