[SeaBIOS] [PATCH 1/4] pci: add two-pass pci initialization code
Gerd Hoffmann
kraxel at redhat.com
Fri Jun 24 17:24:35 CEST 2011
This patch adds a second device scan to the pci initialization, which
counts the memory bars of the various sizes and types. Then it
calculates the sizes and the packing of the prefetchable and
non-prefetchable pci memory windows and prints the results.
The patch doesn't actually map the devices to make debugging easier.
Signed-off-by: Gerd Hoffmann <kraxel at redhat.com>
---
src/pci.h | 8 +
src/pciinit.c | 416 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++-
2 files changed, 421 insertions(+), 3 deletions(-)
diff --git a/src/pci.h b/src/pci.h
index a21a1fd..868752d 100644
--- a/src/pci.h
+++ b/src/pci.h
@@ -3,6 +3,9 @@
#include "types.h" // u32
+#define PCI_ROM_SLOT 6
+#define PCI_NUM_REGIONS 7
+
static inline u8 pci_bdf_to_bus(u16 bdf) {
return bdf >> 8;
}
@@ -48,6 +51,11 @@ struct pci_device {
u8 prog_if, revision;
u8 header_type;
u8 secondary_bus;
+ struct {
+ u32 addr;
+ u32 size;
+ int is64;
+ } r[PCI_NUM_REGIONS];
// Local information on device.
int have_driver;
diff --git a/src/pciinit.c b/src/pciinit.c
index bfff3db..80bc7ad 100644
--- a/src/pciinit.c
+++ b/src/pciinit.c
@@ -6,21 +6,88 @@
// This file may be distributed under the terms of the GNU LGPLv3 license.
#include "util.h" // dprintf
+#include "memmap.h" // e820
#include "pci.h" // pci_config_readl
#include "biosvar.h" // GET_EBDA
#include "pci_ids.h" // PCI_VENDOR_ID_INTEL
#include "pci_regs.h" // PCI_COMMAND
#include "xen.h" // usingXen
-#define PCI_ROM_SLOT 6
-#define PCI_NUM_REGIONS 7
+#define PCI_IO_INDEX_SHIFT 2
+#define PCI_MEM_INDEX_SHIFT 12
-static void pci_bios_init_device_in_bus(int bus);
+#define PCI_BRIDGE_IO_MIN 0x100
+#define PCI_BRIDGE_MEM_MIN 0x100000
static struct pci_region pci_bios_io_region;
static struct pci_region pci_bios_mem_region;
static struct pci_region pci_bios_prefmem_region;
+static struct {
+ u32 start;
+ u32 end;
+} mem_holes[2];
+static int mem_holes_count;
+
+static struct pci_bus {
+ /* pci region stats */
+ u32 io_count[16 - PCI_IO_INDEX_SHIFT];
+ u32 mem_count[32 - PCI_MEM_INDEX_SHIFT];
+ u32 prefmem_count[32 - PCI_MEM_INDEX_SHIFT];
+ u32 io_sum, io_max;
+ u32 mem_sum, mem_max;
+ u32 prefmem_sum, prefmem_max;
+ /* seconday bus region sizes */
+ u32 io_size, mem_size, prefmem_size;
+ /* pci region assignments */
+ u32 io_bases[16 - PCI_IO_INDEX_SHIFT];
+ u32 mem_bases[32 - PCI_MEM_INDEX_SHIFT];
+ u32 prefmem_bases[32 - PCI_MEM_INDEX_SHIFT];
+ u32 io_base, mem_base, prefmem_base;
+} *busses;
+static int busses_count;
+
+static void pci_bios_init_device_in_bus(int bus);
+static void pci_bios_check_device_in_bus(int bus);
+static void pci_bios_init_bus_bases(struct pci_bus *bus);
+static void pci_bios_map_device_in_bus(int bus);
+
+static int pci_size_to_index(u32 size, int shift)
+{
+ int index = __fls(size);
+
+ if (index < shift)
+ index = shift;
+ index -= shift;
+ return index;
+}
+
+static u32 pci_size_roundup(u32 size)
+{
+ int index = pci_size_to_index(size, 0);
+ return 1 << index;
+}
+
+static int pci_io_size_to_index(u32 size)
+{
+ return pci_size_to_index(size, PCI_IO_INDEX_SHIFT);
+}
+
+static u32 pci_io_index_to_size(int index)
+{
+ return 1 << (index + PCI_IO_INDEX_SHIFT);
+}
+
+static int pci_mem_size_to_index(u32 size)
+{
+ return pci_size_to_index(size, PCI_MEM_INDEX_SHIFT);
+}
+
+static u32 pci_mem_index_to_size(int index)
+{
+ return 1 << (index + PCI_MEM_INDEX_SHIFT);
+}
+
/* host irqs corresponding to PCI irqs A-D */
const u8 pci_irqs[4] = {
10, 10, 11, 11
@@ -440,6 +507,328 @@ pci_bios_init_bus(void)
{
u8 pci_bus = 0;
pci_bios_init_bus_rec(0 /* host bus */, &pci_bus);
+ busses_count = pci_bus + 1;
+ busses = malloc_tmphigh(busses_count * sizeof(struct pci_bus));
+}
+
+static void pci_bios_bus_get_bar(struct pci_bus *bus, int bdf, int bar,
+ u32 *val, u32 *size)
+{
+ u32 ofs = pci_bar(bdf, bar);
+ u32 old = pci_config_readl(bdf, ofs);
+ u32 mask;
+
+ if (bar == PCI_ROM_SLOT) {
+ mask = PCI_ROM_ADDRESS_MASK;
+ pci_config_writel(bdf, ofs, mask);
+ } else {
+ if (old & PCI_BASE_ADDRESS_SPACE_IO)
+ mask = PCI_BASE_ADDRESS_IO_MASK;
+ else
+ mask = PCI_BASE_ADDRESS_MEM_MASK;
+ pci_config_writel(bdf, ofs, ~0);
+ }
+ *val = pci_config_readl(bdf, ofs);
+ pci_config_writel(bdf, ofs, old);
+ *size = (~(*val & mask)) + 1;
+}
+
+static void pci_bios_bus_reserve(struct pci_bus *bus, u32 val, u32 size)
+{
+ u32 index;
+
+ if (val & PCI_BASE_ADDRESS_SPACE_IO) {
+ index = pci_io_size_to_index(size);
+ size = pci_io_index_to_size(index);
+ bus->io_count[index]++;
+ bus->io_sum += size;
+ if (bus->io_max < size)
+ bus->io_max = size;
+ } else {
+ index = pci_mem_size_to_index(size);
+ size = pci_mem_index_to_size(index);
+ if (val & PCI_BASE_ADDRESS_MEM_PREFETCH) {
+ bus->prefmem_count[index]++;
+ bus->prefmem_sum += size;
+ if (bus->prefmem_max < size)
+ bus->prefmem_max = size;
+ } else {
+ bus->mem_count[index]++;
+ bus->mem_sum += size;
+ if (bus->mem_max < size)
+ bus->mem_max = size;
+ }
+ }
+}
+
+static u32 pci_bios_bus_get_addr(struct pci_bus *bus, u32 val, u32 size)
+{
+ u32 index, addr;
+
+ if (val & PCI_BASE_ADDRESS_SPACE_IO) {
+ index = pci_io_size_to_index(size);
+ addr = bus->io_bases[index];
+ bus->io_bases[index] += pci_io_index_to_size(index);
+ } else {
+ index = pci_mem_size_to_index(size);
+ if (val & PCI_BASE_ADDRESS_MEM_PREFETCH) {
+ addr = bus->prefmem_bases[index];
+ bus->prefmem_bases[index] += pci_mem_index_to_size(index);
+ } else {
+ addr = bus->mem_bases[index];
+ bus->mem_bases[index] += pci_mem_index_to_size(index);
+ }
+ }
+ return addr;
+}
+
+static void pci_bios_check_device(struct pci_bus *bus, struct pci_device *dev)
+{
+ u16 bdf = dev->bdf;
+ int i;
+
+ if (dev->class == PCI_CLASS_BRIDGE_PCI) {
+ if (dev->secondary_bus >= busses_count) {
+ /* should never trigger */
+ dprintf(1, "PCI: bus count too small (%d), skipping bus #%d\n",
+ busses_count, dev->secondary_bus);
+ return;
+ }
+ struct pci_bus *s = busses + dev->secondary_bus;
+ pci_bios_check_device_in_bus(dev->secondary_bus);
+ s->io_size = pci_size_roundup(s->io_sum);
+ s->mem_size = pci_size_roundup(s->mem_sum);
+ s->prefmem_size = pci_size_roundup(s->prefmem_sum);
+ if (s->io_size < PCI_BRIDGE_IO_MIN) {
+ s->io_size = PCI_BRIDGE_IO_MIN;
+ }
+ if (s->mem_size < PCI_BRIDGE_MEM_MIN) {
+ s->mem_size = PCI_BRIDGE_MEM_MIN;
+ }
+ if (s->prefmem_size < PCI_BRIDGE_MEM_MIN) {
+ s->prefmem_size = PCI_BRIDGE_MEM_MIN;
+ }
+ dprintf(1, "PCI: secondary bus %d sizes: io %x, mem %x, prefmem %x\n",
+ dev->secondary_bus, s->io_size, s->mem_size, s->prefmem_size);
+ pci_bios_bus_reserve(bus, PCI_BASE_ADDRESS_SPACE_IO, s->io_size);
+ pci_bios_bus_reserve(bus, 0, s->mem_size);
+ pci_bios_bus_reserve(bus, PCI_BASE_ADDRESS_MEM_PREFETCH, s->prefmem_size);
+ return;
+ }
+
+ for (i = 0; i < PCI_NUM_REGIONS; i++) {
+ u32 val, size;
+ pci_bios_bus_get_bar(bus, bdf, i, &val, &size);
+ if (val == 0) {
+ continue;
+ }
+ pci_bios_bus_reserve(bus, val, size);
+ dev->r[i].addr = val;
+ dev->r[i].size = size;
+ dev->r[i].is64 = (!(val & PCI_BASE_ADDRESS_SPACE_IO) &&
+ (val & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == PCI_BASE_ADDRESS_MEM_TYPE_64);
+
+ if (dev->r[i].is64) {
+ i++;
+ }
+ }
+}
+
+static void pci_bios_map_device(struct pci_bus *bus, struct pci_device *dev)
+{
+ int i;
+
+ if (dev->class == PCI_CLASS_BRIDGE_PCI) {
+ if (dev->secondary_bus >= busses_count) {
+ return;
+ }
+ struct pci_bus *s = busses + dev->secondary_bus;
+ s->io_base = pci_bios_bus_get_addr
+ (bus, PCI_BASE_ADDRESS_SPACE_IO, s->io_size);
+ s->mem_base = pci_bios_bus_get_addr
+ (bus, 0, s->mem_size);
+ s->prefmem_base = pci_bios_bus_get_addr
+ (bus, PCI_BASE_ADDRESS_MEM_PREFETCH, s->prefmem_size);
+ dprintf(1, "PCI: init bases bus %d (secondary)\n", dev->secondary_bus);
+ pci_bios_init_bus_bases(s);
+ /* TODO: commit assignments */
+ pci_bios_map_device_in_bus(dev->secondary_bus);
+ return;
+ }
+
+ for (i = 0; i < PCI_NUM_REGIONS; i++) {
+ u32 addr;
+ if (dev->r[i].addr == 0) {
+ continue;
+ }
+
+ addr = pci_bios_bus_get_addr(bus, dev->r[i].addr, dev->r[i].size);
+ dprintf(1, " bar %d, addr %x, size %x [%s]\n",
+ i, addr, dev->r[i].size,
+ dev->r[i].addr & PCI_BASE_ADDRESS_SPACE_IO ? "io" : "mem");
+ /* TODO: commit assignments */
+
+ if (dev->r[i].is64) {
+ i++;
+ }
+ }
+}
+
+static void pci_bios_check_device_in_bus(int bus)
+{
+ struct pci_device *pci;
+
+ dprintf(1, "PCI: check devices bus %d\n", bus);
+ foreachpci(pci) {
+ if (pci->rootbus != bus)
+ continue;
+ pci_bios_check_device(&busses[bus], pci);
+ }
+}
+
+static void pci_bios_map_device_in_bus(int bus)
+{
+ struct pci_device *pci;
+
+ foreachpci(pci) {
+ if (pci->rootbus != bus)
+ continue;
+ dprintf(1, "PCI: map device bus %d, bfd 0x%x\n", bus, pci->bdf);
+ pci_bios_map_device(&busses[bus], pci);
+ }
+}
+
+static void pci_bios_init_bus_bases(struct pci_bus *bus)
+{
+ u32 base, newbase, size;
+ int i;
+
+ /* assign prefetchable memory regions */
+ dprintf(1, " prefmem max %x sum %x base %x\n",
+ bus->prefmem_max, bus->prefmem_sum, bus->prefmem_base);
+ base = bus->prefmem_base;
+ for (i = ARRAY_SIZE(bus->prefmem_count)-1; i >= 0; i--) {
+ size = pci_mem_index_to_size(i);
+ if (!bus->prefmem_count[i])
+ continue;
+ newbase = base + size * bus->prefmem_count[i];
+ dprintf(1, " size %8x: %d bar(s), %8x -> %8x\n",
+ size, bus->prefmem_count[i], base, newbase - 1);
+ bus->prefmem_bases[i] = base;
+ base = newbase;
+ }
+
+ /* assign memory regions */
+ dprintf(1, " mem max %x sum %x base %x\n",
+ bus->mem_max, bus->mem_sum, bus->mem_base);
+ base = bus->mem_base;
+ for (i = ARRAY_SIZE(bus->mem_count)-1; i >= 0; i--) {
+ size = pci_mem_index_to_size(i);
+ if (!bus->mem_count[i])
+ continue;
+ newbase = base + size * bus->mem_count[i];
+ dprintf(1, " mem size %8x: %d bar(s), %8x -> %8x\n",
+ size, bus->mem_count[i], base, newbase - 1);
+ bus->mem_bases[i] = base;
+ base = newbase;
+ }
+
+ /* assign io regions */
+ dprintf(1, " io max %x sum %x base %x\n",
+ bus->io_max, bus->io_sum, bus->io_base);
+ base = bus->io_base;
+ for (i = ARRAY_SIZE(bus->io_count)-1; i >= 0; i--) {
+ size = pci_io_index_to_size(i);
+ if (!bus->io_count[i])
+ continue;
+ newbase = base + size * bus->io_count[i];
+ dprintf(1, " io size %4x: %d bar(s), %4x -> %4x\n",
+ size, bus->io_count[i], base, newbase - 1);
+ bus->io_bases[i] = base;
+ base = newbase;
+ }
+}
+
+#define ROOT_BASE(top, sum, align) ALIGN_DOWN((top)-(sum),(align))
+
+static int pci_bios_init_root_regions(void)
+{
+ struct pci_bus *bus = &busses[0];
+ int h1, h2;
+
+ /* io ports */
+ bus->io_base = 0xc000;
+
+ /* try to fit all into one memory hole */
+ for (h1 = mem_holes_count-1; h1 >= 0; h1--) {
+ if (bus->mem_sum < bus->prefmem_sum) {
+ bus->mem_base = ROOT_BASE(mem_holes[h1].end,
+ bus->mem_sum, bus->mem_max);
+ bus->prefmem_base = ROOT_BASE(bus->mem_base,
+ bus->prefmem_sum, bus->prefmem_max);
+ if (bus->prefmem_base >= mem_holes[h1].start) {
+ return 0;
+ }
+ } else {
+ bus->prefmem_base = ROOT_BASE(mem_holes[h1].end,
+ bus->prefmem_sum, bus->prefmem_max);
+ bus->mem_base = ROOT_BASE(bus->prefmem_base,
+ bus->mem_sum, bus->mem_max);
+ if (bus->mem_base >= mem_holes[h1].start) {
+ return 0;
+ }
+ }
+ }
+
+ if (mem_holes_count <= 1) {
+ /* can't try to split -> OOM */
+ return -1;
+ }
+
+ /* try to fit the larger one first */
+ for (h1 = mem_holes_count-1; h1 >= 0; h1--) {
+ if (bus->mem_sum < bus->prefmem_sum) {
+ bus->prefmem_base = ROOT_BASE(mem_holes[h1].end,
+ bus->prefmem_sum, bus->prefmem_max);
+ if (bus->prefmem_base >= mem_holes[h1].start) {
+ break;
+ }
+ } else {
+ bus->mem_base = ROOT_BASE(mem_holes[h1].end,
+ bus->mem_sum, bus->mem_max);
+ if (bus->mem_base >= mem_holes[h1].start) {
+ break;
+ }
+ }
+ }
+
+ if (h1 == -1) {
+ /* all holes too small -> OOM */
+ return -1;
+ }
+
+ /* try to fit the smaller one now */
+ for (h2 = mem_holes_count-1; h2 >= 0; h2--) {
+ if (h1 == h2) {
+ continue; /* hole already taken */
+ }
+ if (bus->mem_sum < bus->prefmem_sum) {
+ bus->mem_base = ROOT_BASE(mem_holes[h2].end,
+ bus->mem_sum, bus->mem_max);
+ if (bus->mem_base >= mem_holes[h2].start) {
+ return 0;
+ }
+ } else {
+ bus->prefmem_base = ROOT_BASE(mem_holes[h2].end,
+ bus->prefmem_sum, bus->prefmem_max);
+ if (bus->prefmem_base >= mem_holes[h2].start) {
+ return 0;
+ }
+ }
+ }
+
+ /* didn't work out ... */
+ return -1;
}
void
@@ -453,19 +842,40 @@ pci_setup(void)
dprintf(3, "pci setup\n");
+ /* matches acpi-dsdt.dsl */
+ mem_holes[0].start = 0xe0000000;
+ mem_holes[0].end = BUILD_IOAPIC_ADDR;
+ mem_holes_count = 1;
+
pci_region_init(&pci_bios_io_region, 0xc000, 64 * 1024 - 1);
pci_region_init(&pci_bios_mem_region,
BUILD_PCIMEM_START, BUILD_PCIMEM_END - 1);
pci_region_init(&pci_bios_prefmem_region,
BUILD_PCIPREFMEM_START, BUILD_PCIPREFMEM_END - 1);
+ dprintf(1, "=== PCI bus & bridge init ===\n");
pci_bios_init_bus();
+ dprintf(1, "=== PCI device probing ===\n");
pci_probe();
+ dprintf(1, "=== PCI new allocation pass #1 ===\n");
+ pci_bios_check_device_in_bus(0 /* host bus */);
+ if (pci_bios_init_root_regions() != 0) {
+ dprintf(1, "PCI: out of address space\n");
+ /* Hmm, what do now? */
+ }
+
+ dprintf(1, "=== PCI new allocation pass #2 ===\n");
+ pci_bios_map_device_in_bus(0 /* host bus */);
+
+ dprintf(1, "=== PCI old allocation pass ===\n");
struct pci_device *pci;
foreachpci(pci) {
pci_init_device(pci_isa_bridge_tbl, pci, NULL);
}
pci_bios_init_device_in_bus(0 /* host bus */);
+
+ free(busses);
+ busses_count = 0;
}
--
1.7.1
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