[SeaBIOS] Graphics card pass-through working with two pass pci-initialization

[Jan Kiszka]

On 2011-06-01 16:20, Isaku Yamahata wrote:
> On Wed, Jun 01, 2011 at 09:30:12AM +0200, Gerd Hoffmann wrote:
>>   Hi,
>>
>>> 0xE0000000 is hard-coded in the DSDT for both piix and q35 as below.
>>> If the range is determined dynamically, the area also needs to be
>>> updated somehow dynamically.
>>>
>>> ...
>>>              Name (_CRS, ResourceTemplate ()
>>> ...
>>>                  DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
>>>                      0x00000000,         // Address Space Granularity
>>>                      0xE0000000,         // Address Range Minimum
>>>                      0xFEBFFFFF,         // Address Range Maximum
>>>                      0x00000000,         // Address Translation Offset
>>>                      0x1EC00000,         // Address Length
>>>                      ,, , AddressRangeMemory, TypeStatic)
>>
>> Uhm, indeed.  I know next to nothing about ACPI though.  Ideas anyone  
>> how this could be done?
> 
> Right now what I can think of is.
> It would be possible to know the offset in AmlCode[] by
> compiling dsl with -l option. The we can get the mix of source and
> resulted hex with offset like
> 
> iasl -l q35-acpi-dsdt.dsl.i
> => q35-acpi-dsdt.dsl.lst
> 
>      192....                DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
>      193....                    0x00000000,
>      194....                    0xE0000000,
>      195....                    0xFEBFFFFF,
>      196....                    0x00000000,
>      197....                    0x1EC00000,
>      198....                    ,, , AddressRangeMemory, TypeStatic)
> 
> 00000F74....87 17 00 00 0C 01 00 00     "........"
> 00000F7C....00 00 00 00 00 E0 FF FF     "........"
> 00000F84....BF FE 00 00 00 00 00 00     "........"
> 00000F8C....C0 1E ..................    ".."
> 00000F8E....79 00 ..................    "y."
> 
> But this is very iasl specific and fragile...

Why make this particular thing dynamic? Physical PCs need to define a
certain fixed PCI memory region as well and then live with it. IMHO, the
current setting is just too small for normal use.

Jan

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