[SeaBIOS] [PATCH 0/7] ahci update

[Kevin O'Connor]

On Mon, Jul 18, 2011 at 12:26:41PM -0600, Marc Jones wrote:
> On Sun, Jul 17, 2011 at 8:16 AM, Kevin O'Connor <kevin at koconnor.net> wrote:
> > I've confirmed that with this patch series applied I can boot my
> > Asrock e350m1 board in AHCI mode.
> You tested that by changing SATA_MODE in cfg.h?

Yes - I used the patch below to enable AHCI mode in coreboot.

>If it is working and
> commited, we should make ahci the default in coreboot.

I have not yet committed the AHCI patch series.

However, SeaBIOS can now handle the sb800 in AHCI mode with its
regular ATA support.  (A previous committed patch enables the the ATA
driver to recognize that the AMD ahci controller can be driven as an
ATA device when AHCI is disabled in SeaBIOS.)

-Kevin


diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c
index 0a09e11..36136b4 100644
--- a/src/southbridge/amd/cimx/sb800/cfg.c
+++ b/src/southbridge/amd/cimx/sb800/cfg.c
@@ -83,7 +83,7 @@ void sb800_cimx_config(AMDSBCFG *sb_config)
   	sb_config->SATAMODE.SataMode.SataController = SATA_CONTROLLER;
 	sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary, 1 -IDE as secondary.
 								//TODO: set to secondary not take effect.
-	sb_config->SATAMODE.SataMode.SataIdeCombinedMode = 0; //IDE controlor exposed and combined mode enabled
+	sb_config->SATAMODE.SataMode.SataIdeCombinedMode = 1; //IDE controlor exposed and combined mode enabled
 	sb_config->SATAMODE.SataMode.SATARefClkSel = SATA_CLOCK_SOURCE;
 
   	/* Azalia HDA */
diff --git a/src/southbridge/amd/cimx/sb800/cfg.h b/src/southbridge/amd/cimx/sb800/cfg.h
index 05db9ab..581fc66 100644
--- a/src/southbridge/amd/cimx/sb800/cfg.h
+++ b/src/southbridge/amd/cimx/sb800/cfg.h
@@ -109,7 +109,7 @@
  *   NOTE: DO NOT ALLOW SATA & IDE use same mode
  */
 #ifndef SATA_MODE
-  #define SATA_MODE			NATIVE_IDE_MODE
+  #define SATA_MODE			AHCI_MODE
 #endif
 
 /**