[SeaBIOS] ohci bulk?
H. Peter Anvin
hpa at zytor.com
Mon Nov 22 17:50:00 CET 2010
On 11/22/2010 07:45 AM, Avi Kivity wrote:
> Correct. Note, it's likely that we have almost everything covered
> already, so it's mostly testing (beyond implementing SMM entry/exit).
> However, we have a large deployed base with no SMM support, so we need a
> fallback if SMM is not available. It's also tricky to probe for working
> SMM, I don't think there's a cpuid bit for that.
All real CPUs 586+ support SMM, so a CPUID bit wouldn't be applicable.
That being said, SMM has to be activated from the chipset, so some kind
of ID bit could be put in there.
H. Peter Anvin, Intel Open Source Technology Center
I work for Intel. I don't speak on their behalf.
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