[SeaBIOS] ohci bulk?

Gerd Hoffmann kraxel at redhat.com
Mon Nov 22 11:52:56 CET 2010


>> Would INT 15h, AH=87h do the job well enough?

Someone mentioned earlier in this thread that one does 16bit memory 
access whereas pci memory bars are usually accessed using 32bit 
read/writes ...

> I suppose one could implement a simple SMM gateway - write a magic IO
> bit to invoke the SMM handler, have the SMM handler backup the cpu
> state somewhere in BIOS owned memory, and then leave SMM mode with
> execution at a BIOS handler running in 32bit flat mode.

Hmm, how about having a virtual "I/O bounce" device?  Allocate two 
dwords in I/O space.  One dword for the address, one for the data. reads 
and writes to the data register will be bounced to the address written 
into the address register.

On real hardware seabios could emulate this using SMM.

On virtual hardware qemu could emulate this so we don't need SMM support 
in kvm.

 From a security point of view it might not be the best idea though.



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