[openfirmware] [commit] r3634 - cpu/arm/olpc

[repository service]

Author: quozl
Date: Tue Apr  2 04:49:01 2013
New Revision: 3634
URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3634

Log:
OLPC XO-1.75 XO-4 - rely on the RTC register oscillator stop flag to signal when to reinitialise the data.  However, already manufactured laptops do not have the oscillator stop flag in the RTC registers cleared, so detect these by absence of a "cv" tag, and add the tag once the flag has been reset.

Modified:
   cpu/arm/olpc/build-fw.fth
   cpu/arm/olpc/rtc.fth

Modified: cpu/arm/olpc/build-fw.fth
==============================================================================
--- cpu/arm/olpc/build-fw.fth	Tue Apr  2 04:46:16 2013	(r3633)
+++ cpu/arm/olpc/build-fw.fth	Tue Apr  2 04:49:01 2013	(r3634)
@@ -221,6 +221,12 @@
 
 fload ${BP}/dev/olpc/spiflash/spiui.fth      \ User interface for SPI FLASH programming
 \ fload ${BP}/dev/olpc/spiflash/recover.fth    \ XO-to-XO SPI FLASH recovery
+
+\ This must be defined after spiui.fth,
+\ otherwise spiui will choose some wrong code
+: rom-pa  ( -- adr )  mfg-data-buf mfg-data-offset -  ;  \ Fake out setwp.fth
+fload ${BP}/cpu/x86/pc/olpc/setwp.fth
+
 : ofw-fw-filename$  " disk:\boot\olpc.rom"  ;
 ' ofw-fw-filename$ to fw-filename$
 
@@ -321,6 +327,16 @@
    " /i2c at d4031000/rtc" open-dev  clock-node !
    \ use RTC 32kHz clock as SoC external slow clock
    h# 38 mpmu@ 1 or h# 38 mpmu!
+   \ if the clock valid tag is absent, clear the stop flag and add the tag
+   " cv" find-tag  0=  if
+      ." RTC oscillator stop flag one-off wipe (no cv tag)" cr
+      " unstop" clock-node @ $call-method
+      " "(00)" " cv" $add-tag \ a reboot expected here
+      begin wfi again
+   then
+   2drop
+   \ check the clock stop flag and reinit if necessary
+   " verify" clock-node @ $call-method
 ;
 
 warning @ warning off
@@ -590,10 +606,6 @@
 ' linux-hook-emmc to linux-hook
 [then]
 
-\ This must be defined after spiui.fth, otherwise spiui will choose some wrong code
-: rom-pa  ( -- adr )  mfg-data-buf mfg-data-offset -  ;  \ Fake out setwp.fth
-fload ${BP}/cpu/x86/pc/olpc/setwp.fth
-
 fload ${BP}/cpu/arm/olpc/help.fth
 fload ${BP}/cpu/x86/pc/olpc/gui.fth
 fload ${BP}/cpu/x86/pc/olpc/via/mfgtest.fth

Modified: cpu/arm/olpc/rtc.fth
==============================================================================
--- cpu/arm/olpc/rtc.fth	Tue Apr  2 04:46:16 2013	(r3633)
+++ cpu/arm/olpc/rtc.fth	Tue Apr  2 04:49:01 2013	(r3634)
@@ -12,7 +12,18 @@
 
 headerless
 
-: reinit
+\ if the oscillator stop flag is set the RTC counter and RTC SRAM
+\ contents cannot be trusted.
+
+: stopped?  ( -- stopped? )  \ check the oscillator stop flag
+   7 rtc@ h# 20 and
+;
+
+: unstop  ( -- )  \ clear the oscillator stop flag
+   7 rtc@ h# 20 invert and 7 rtc!
+;
+
+: reinit  \ reinitialise the RTC counter
    h# 20 h#  8 rtc! \ century
    h# 13 h#  6 rtc! \ year
    h#  1 h#  5 rtc! \ month
@@ -24,15 +35,28 @@
    ." RTC cleared" cr
 ;
 
-: ?clear
-   h# 3f rtc@  h# 3e rtc@  bwjoin  h# 55aa  <>  if
-      h# 20 h# 10  do  0 i rtc!  loop  \ wipe cmos@ cmos! area
-      h# 55aa  wbsplit  h# 3e rtc!  h# 3f rtc!
-      ." RTC SRAM cleared" cr
-   then
+h# 55aa value sram-marker  \ our magic marker for RTC SRAM
+
+: sram-corrupt?  ( -- corrupt? )  \ is the RTC SRAM corrupt?
+   h# 3f rtc@  h# 3e rtc@  bwjoin  sram-marker  <>
+;
+
+: sram-reinit  ( -- )  \ reinitialise the RTC SRAM
+   h# 20 h# 10  do  0 i rtc!  loop  \ wipe cmos@ cmos! area
+   sram-marker  wbsplit  h# 3e rtc!  h# 3f rtc!
+   ." RTC SRAM cleared" cr
 ;
 
 headers
+: verify  ( -- )  \ check RTC for loss of data and reinitialise if so
+   stopped?  if
+      \ RTC says data is lost
+      [ifndef] olpc-cl2  reinit  [then]  \ requested by Daniel Drake
+      unstop
+   then
+   sram-corrupt?  if  sram-reinit  reinit  then
+;
+
 : open  ( -- okay )
    my-unit " set-address" $call-parent
 
@@ -52,15 +76,6 @@
       drop true                ( true )
    then                        ( okay? )
 
-   \ check and clear the oscillator stop flag
-   7 rtc@ h# 20 and  if
-      reinit
-      7 rtc@ h# 20 invert and 7 rtc!
-   then
-
-   \ manage legacy RTC CMOS usage
-   ?clear
-
    \ enable 32kHz clock output
    h# b3 7 rtc!
 ;