[openfirmware] [commit] r3427 - in cpu/arm: mmp2 mmp3
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svn at openfirmware.info
Wed Nov 14 22:51:35 CET 2012
Author: wmb
Date: Wed Nov 14 22:51:30 2012
New Revision: 3427
URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3427
Log:
OLPC ARM MMP3 - Fixed suspend (it didn't sleep fully in Q7B05) by undoing the svn 3410 change in pcr! , and finished moving the wakeup configuration code out of the go-to-sleep code.
Modified:
cpu/arm/mmp2/rtc.fth
cpu/arm/mmp2/wakeups.fth
cpu/arm/mmp3/dramrecal.fth
Modified: cpu/arm/mmp2/rtc.fth
==============================================================================
--- cpu/arm/mmp2/rtc.fth Wed Nov 14 08:47:41 2012 (r3426)
+++ cpu/arm/mmp2/rtc.fth Wed Nov 14 22:51:30 2012 (r3427)
@@ -20,7 +20,12 @@
: enable-rtc ( -- ) h# 81 0 apbc! ; \ Turn on the clock for the internal RTC
: enable-rtc-wakeup ( -- )
- h# 2.0010 h# 104c +mpmu io-set
+ h# 2.0010 h# 104c +mpmu io-set \ Unmask wakeup 4 (10) and RTC (20000) in PMUM_WUCRM_PJ
+
+ \ Disabling a wakeup decoder in either PCR register disables that wakeup,
+ \ so we must clear the bit in both registers to allow it.
+ h# 4.0000 h# 1000 +mpmu io-clr \ Unmask wakeup 4 decoder in PMUM_PCR_PJ
+ h# 4.0000 h# 0 +mpmu io-clr \ Unmask wakeup 4 decoder in PMUM_PCR_SP
;
: soc-rtc@ ( offset -- value ) h# 01.0000 + io@ ;
: soc-rtc! ( value offset -- value ) h# 01.0000 + io! ;
Modified: cpu/arm/mmp2/wakeups.fth
==============================================================================
--- cpu/arm/mmp2/wakeups.fth Wed Nov 14 08:47:41 2012 (r3426)
+++ cpu/arm/mmp2/wakeups.fth Wed Nov 14 22:51:30 2012 (r3427)
@@ -1,6 +1,29 @@
\ See license at end of file
purpose: Setup keyboard wakeups and display the state of the wakeup machinery
+0 [if]
+: pcr-clr ( mask -- ) dup h# 00 mpmu-clr h# 1000 mpmu-clr ;
+
+create wakeup-masks \ Bits in MPMU+0 and MPMU+1000, indexed by wakeup port number
+ h# 0080.0000 , h# 0040.0000 , h# 0020.0000 , h# 0010.0000 ,
+ h# 0004.0000 , h# 0002.0000 , h# 0001.0000 , h# 0000.8000 ,
+
+: port>bit ( port# -- ) wakeup-masks swap na+ @ ;
+
+: wucrm-set ( mask -- ) dup h# 4c mpmu-set h# 104c mpmu-set ;
+
+\ We enable the wakeup port in both the SP and PJ registers, thus avoiding
+\ any ambiguity about whether the bits are ORed or ANDed
+: wakeup-port-on ( port# -- )
+ dup port>bit pcr-clr
+ 1 swap lshift wucrm-set
+;
+: rtc-wakeup-on ( -- )
+ h# 2.0000 wucrm-set
+ 4 wakeup-port-on
+;
+[then]
+
\ XXX we might need to set GPIOs 71 and 160 (ps2 clocks), and perhaps the dat lines too,
\ for non-sleep-mode control - or maybe for sleep mode control as inputs.
\ We also may need to enable falling edge detects.
Modified: cpu/arm/mmp3/dramrecal.fth
==============================================================================
--- cpu/arm/mmp3/dramrecal.fth Wed Nov 14 08:47:41 2012 (r3426)
+++ cpu/arm/mmp3/dramrecal.fth Wed Nov 14 22:51:30 2012 (r3427)
@@ -128,6 +128,12 @@
: cc4-set ( mask -- ) h# 248 pmua-set ;
: cc4-clr ( mask -- ) h# 248 pmua-clr ;
+\ PXA2128_Registers_Manual_revF.pdf says to always write 0 to bits [14:0]
+\ of MPMU+0x1000, but, empirically, that prevents deep sleep. Apparently
+\ bits [14:13] are legacy bits like in MPMU+0x0
+: pcr! ( value -- ) dup h# 00 mpmu! h# 1000 mpmu! ;
+: pcr-set ( mask -- ) dup h# 00 mpmu-set h# 1000 mpmu-set ;
+
0 [if]
: pj-c1 ( -- )
h# 62 idle-cfg-clr \ light sleep after WFI
@@ -152,26 +158,15 @@
;
[then]
-create wakeup-masks \ Bits in MPMU+0 and MPMU+1000, indexed by wakeup port number
- h# 0080.0000 , h# 0040.0000 , h# 0020.0000 , h# 0010.0000 ,
- h# 0004.0000 , h# 0002.0000 , h# 0001.0000 , h# 0000.8000 ,
-
-: port>bit ( port# -- ) wakeup-masks swap na+ @ ;
-
-: pcr! ( value -- ) dup h# 00 mpmu! h# 7fff invert and h# 1000 mpmu! ;
-: pcr-set ( mask -- ) dup h# 00 mpmu-set h# 1000 mpmu-set ;
-: pcr-clr ( mask -- ) dup h# 00 mpmu-clr h# 1000 mpmu-clr ;
-: wucrm-set ( mask -- ) dup h# 4c mpmu-set h# 104c mpmu-set ;
+0 value apcr
+: deep-sleep-on ( -- )
+ h# 1000 mpmu@ to apcr
-\ We enable the wakeup port in both the SP and PJ registers, thus avoiding
-\ any ambiguity about whether the bits are ORed or ANDed
-: wakeup-port-on ( port# -- )
- dup port>bit pcr-clr
- 1 swap lshift wucrm-set
+ \ Wakeup ports will be handler at a higher level
+ h# be086000 pcr-set \ AXISD, SPLEN, SPSD, DDRCORSD, APBSD, RSVD, VCXOSD, MSASLPEN, UDR_POWER_OFF_EN \ Step 11
;
-: deep-sleep-on ( -- )
- \ Start with all wakeup ports masked off, enable specific ones later
- h# beffe000 pcr! \ AXISD, SPLEN, SPSD, DDRCORSD, APBSD, RSVD, VCXOSD, MSASLPEN, UDR_POWER_OFF_EN \ Step 11
+: deep-sleep-off ( -- )
+ apcr h# 1000 mpmu!
;
\ D2_L2_PWD 462
@@ -183,10 +178,6 @@
idle-cfg@ h# 0def.fc1d and ( mask kept )
or idle-cfg! ( )
;
-: rtc-wakeup-on ( -- )
- h# 2.0000 wucrm-set
- 4 wakeup-port-on
-;
code outer-flush-all ( -- )
c;
code flush-cache-all
@@ -251,16 +242,12 @@
1 h# 2190 icu! \ ICU_GBL_IRQ6_MSK
;
-0 value apcr
: setup-sleep-state ( -- )
sp-c1-on
make-ddr3-recal-tables
- h# 1000 mpmu@ to apcr
-
deep-sleep-on
-\ rtc-wakeup-on \ Unnecessary; alarm-in-3 does it
h# 462 set-idle \ D2_L2_PWD
@@ -270,8 +257,6 @@
\ I don't think we need this because L2 is off
\ h# 8000 cc4-set \ workaround: keep SL2 power on
-\ wakeup-irqs-on \ Unnecessary; alarm-in-3 does it
-
global-irqs-off
flush-cache-all
@@ -281,15 +266,13 @@
\ mp-off
;
: restore-run-state ( -- )
- wakeup-irqs-off
-
\ fw-on
\ mp-on
\ I don't think we need this because L2 is off
\ h# 8000 cc4-clr \ workaround: keep SL2 power on
- apcr h# 1000 mpmu!
+ deep-sleep-off
h# 8000.0000 idle-cfg-set \ Workaround: restore AT clock
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