[openfirmware] r1356 - cpu/x86/pc/olpc/via

[svn at openfirmware.info]

Author: wmb
Date: 2009-09-10 10:07:14 +0200 (Thu, 10 Sep 2009)
New Revision: 1356

Modified:
   cpu/x86/pc/olpc/via/romreset.bth
   cpu/x86/pc/olpc/via/startcominit.fth
Log:
Via early startup -
1) Fixed version sensing via EC - needed to enable
   I/O decoding for the special EC port
2) Moved the startup delay to exactly the required point,
   just before the first CMOS access
3) Restore a couple of registers in D17F7 that are killed during S3.


Modified: cpu/x86/pc/olpc/via/romreset.bth
===================================================================
--- cpu/x86/pc/olpc/via/romreset.bth	2009-09-10 08:04:30 UTC (rev 1355)
+++ cpu/x86/pc/olpc/via/romreset.bth	2009-09-10 08:07:14 UTC (rev 1356)
@@ -92,8 +92,6 @@
 
    fload ${BP}/cpu/x86/pc/olpc/via/startcacheasram.fth
 
-   d# 40000 wait-us \ This delay is empirically necessary - minimum is 36000 - about 50 ms
-
 \ cache_as_ram_auto.c: amd64_main() 
 
    01 004f config-wb   \ Enable device 0 multiple functions
@@ -114,8 +112,6 @@
    cominit #) call
 [then]
 
-   carret report
-   linefeed report
    char + report
    h# 1d port80
 
@@ -127,17 +123,24 @@
    long-offsets on
 
    acpi-io-base 4 + port-rw           \ Get APCI Status register
-   d# 10 # ax shr  7 # ax and  1 # ax cmp  <>  if   \ Wakeup from S3
+   d# 10 # ax shr  7 # ax and  1 # ax cmp  <>  if  \ Type 1 is wakeup from S3
+      \ Not wakeup from S3
       \ This turns an OS reboot into a real cold start - from coreboot
       h# 380 config-rb  ax ax or  0<>  if          \ C-page shadowing not on yet
          6 h# cf9 port-wb                          \ Force a full system reset
          char X report
          begin  hlt  again
       then
+      carret report   linefeed report
       char F report
       fload ${BP}/cpu/x86/pc/olpc/via/demodram.fth
    then
 
+   \ This must be done in both the power-up and resume-from-S3 cases,
+   \ since the registers in D17F7 lose state during S3.
+   total-size  8f60 config-wb  \ DRAM Bank 7 ending address - controls DMA upstream
+   0388 config-rb  ax bx mov  8fe5 config-setup  bx ax mov  al dx out  \ Copy Low Top from RO reg 88 to SB Low Top e5
+
    fload ${BP}/cpu/x86/pc/olpc/via/startgfxinit.fth
 
 0 [if]  \ Fire up C Forth
@@ -171,6 +174,10 @@
    fload ${BP}/cpu/x86/pc/olpc/via/ioinit.fth
 \ XXX need to move startcpuspeed to here
 
+   \ Cache is now setup normally, backed by memory
+   \ Setup a small stack for subroutine calls
+   h# 10.0000 # esp mov
+
    acpi-io-base 4 + port-rw           \ Get APCI Status register
    ax bx mov
    d# 10 # ax shr  7 # ax and  1 # ax cmp  =  if   \ Wakeup from S3
@@ -192,9 +199,6 @@
       char x report
    then                                            \ Not a wakeup from S3
 
-   \ Cache is now setup normally, backed by memory
-   h# 20.0000 # esp mov
-
    char o report
    h# 1e port80
 

Modified: cpu/x86/pc/olpc/via/startcominit.fth
===================================================================
--- cpu/x86/pc/olpc/via/startcominit.fth	2009-09-10 08:04:30 UTC (rev 1355)
+++ cpu/x86/pc/olpc/via/startcominit.fth	2009-09-10 08:07:14 UTC (rev 1356)
@@ -34,6 +34,24 @@
    4e 18 18 mreg  \ Enable ports 74/75 for CMOS RAM access  - 10 res be like Phx
    end-table
 
+   \ Configure the I/O decoding to enable access to the EC
+   \ Do this outside the if..then so the setup is consistent in all cases
+   d# 17 0 devfunc
+   59 ff 1c mreg  \ Keyboard (ports 60,64) and ports 62,66 on LPC bus (EC)
+   5c ff 68 mreg  \ High byte (68) of PCS0
+   5d ff 00 mreg  \ High byte (00) of PCS0
+   64 0f 07 mreg  \ PCS0 size is 8 bytes - to include 68 and 6c
+   66 01 01 mreg  \ PCS0 Enable
+   67 10 10 mreg  \ PCS0 to LPC Bus
+   end-table
+
+   \ This delay is empirically necessary before reading CMOS - minimum is 36000 - about 50 ms
+   \ Before the delay has elapsed, the CMOS RAM returns 0 instead of the stored value.
+   d# 40000 wait-us
+
+   \ As an optimization to avoid long waits for the EC to respond, read the board ID
+   \ that is cached in CMOS RAM.  This might not in fact be an optimization in light
+   \ of the above delay ...
    h# 83 # al mov  al h# 74 # out  h# 75 # al in    \ check byte - should be ~board-id
    al ah mov   ah not                               \ ~check byte in AH
    h# 82 # al mov  al h# 74 # out  h# 75 # al in    \ board-id in AL