[openfirmware] r1435 - cpu/x86/pc/olpc/via dev/olpc/dcon dev/via/unichrome
svn at openfirmware.info
svn at openfirmware.info
Tue Oct 27 21:13:52 CET 2009
Author: wmb
Date: 2009-10-27 21:13:52 +0100 (Tue, 27 Oct 2009)
New Revision: 1435
Modified:
cpu/x86/pc/olpc/via/startgfxrestore.fth
dev/olpc/dcon/viadcon.fth
dev/via/unichrome/unichrome.fth
dev/via/unichrome/vgamodes.fth
Log:
OLPC trac 9472 - suppress display restore on S3 resume in non-native mode.
Modified: cpu/x86/pc/olpc/via/startgfxrestore.fth
===================================================================
--- cpu/x86/pc/olpc/via/startgfxrestore.fth 2009-10-27 16:23:11 UTC (rev 1434)
+++ cpu/x86/pc/olpc/via/startgfxrestore.fth 2009-10-27 20:13:52 UTC (rev 1435)
@@ -26,6 +26,9 @@
e4 48 48 mreg \ Use multifunction pins as GPO10 and GPI10/11
end-table
+long-offsets @ long-offsets on
+native-mode# # video-mode-adr #) cmp = if
+
\ olpc-lcd-mode
c0 1b seq-set \ Secondary engine clock (LCK) can be gated on or off
@@ -116,3 +119,6 @@
ff acpi-io-base 4d + port-wb \ B1 and B2 - DCON LOAD is the 0x04 bit (bit number 2) of PMIO+4d
ff acpi-io-base 4f + port-wb \ A1 and A2 - DCON LOAD is the 0x10 bit (bit number 4) of PMIO+4f
d# 19000 wait-us
+
+then
+long-offsets !
Modified: dev/olpc/dcon/viadcon.fth
===================================================================
--- dev/olpc/dcon/viadcon.fth 2009-10-27 16:23:11 UTC (rev 1434)
+++ dev/olpc/dcon/viadcon.fth 2009-10-27 20:13:52 UTC (rev 1435)
@@ -243,6 +243,7 @@
: init-xo-display ( -- )
smb-init
+ note-native-mode
olpc-lcd-mode
olpc-crt-off
Modified: dev/via/unichrome/unichrome.fth
===================================================================
--- dev/via/unichrome/unichrome.fth 2009-10-27 16:23:11 UTC (rev 1434)
+++ dev/via/unichrome/unichrome.fth 2009-10-27 20:13:52 UTC (rev 1435)
@@ -1,6 +1,6 @@
+\ See license at end of file
purpose: Driver for Via Unichrome Pro, model VX855
-
hex
headers
@@ -16,10 +16,13 @@
d# 16 value depth \ Bits per pixel
d# 1024 value /scanline \ Frame buffer line width
-: set-resolution ( width height depth -- )
- to depth to height to width
-;
+\ This writes a memory variable that the early startup code can find,
+\ so the resume-from-S3 path can do the right thing
+: note-mode ( mode# -- ) video-mode-adr ! ;
+: note-native-mode ( -- ) native-mode# note-mode ;
+: set-resolution ( width height depth -- ) to depth to height to width ;
+
: declare-props ( -- ) \ Instantiate screen properties
" width" get-my-property if
width encode-int " width" property
@@ -51,28 +54,6 @@
fb-va encode-int " address" property
;
-\ \ VGA register access
-\
-\ \ reset attribute address flip-flop
-\ : reset-attr-addr ( -- ) h# 3da ( input-status1 ) pc@ drop ;
-\
-\ : video-mode! ( b -- ) reset-attr-addr h# 03c0 pc! ;
-\ : attr! ( b index -- ) reset-attr-addr h# 03c0 pc! h# 03c0 pc! ;
-\ : attr@ ( index -- b )
-\ reset-attr-addr h# 03c0 pc! h# 03c1 pc@ reset-attr-addr
-\ ;
-\ : grf! ( b index -- ) h# 03ce pc! h# 03cf pc! ;
-\ : grf@ ( index -- b ) h# 03ce pc! h# 03cf pc@ ;
-\
-\ : crt@ ( index -- byte ) h# 3d4 pc! h# 3d5 pc@ ;
-\ : crt! ( byte index -- ) h# 3d4 pc! h# 3d5 pc! ;
-\
-\ : seq@ ( index -- byte ) h# 3c4 pc! h# 3c5 pc@ ;
-\ : seq! ( byte index -- ) h# 3c4 pc! h# 3c5 pc! ;
-\
-\ : misc@ ( -- byte ) h# 3cc pc@ ;
-\ : misc! ( byte -- ) h# 3c2 pc! ;
-
: pll, ( v44 v45 v46 misc -- ) bljoin l, ;
\ Timing table for various resolutions
@@ -113,7 +94,7 @@
\ width height htotal hsync hsyncend vtotal vsync vsyncend --pll-- misc --vckpll---
create mode3-entry
- 640 w, 400 w, 800 w, 688 w, 784 w, 449 w, 413 w, 415 w, hex 03 90 54 67 pll, 04 10 97 00 pll, decimal
+ 640 w, 400 w, 800 w, 688 w, 784 w, 449 w, 413 w, 415 w, hex 85 90 8c 67 pll, 04 10 97 00 pll, decimal
\ This standard timing works but you have to adjust the sync by "06 07 33 crt-mask"
\ 640 w, 400 w, 800 w, 656 w, 752 w, 449 w, 413 w, 415 w, hex 03 90 54 67 pll, 04 10 97 00 pll, decimal
@@ -131,8 +112,7 @@
\ width height htotal hsync hsyncend vtotal vsync vsyncend --pll-- misc --vckpll---
create mode12-entry
-\ 640 w, 480 w, 800 w, 672 w, 768 w, 525 w, 490 w, 492 w, hex 05 04 35 e3 pll, 00 00 00 00 pll, decimal
- 640 w, 480 w, 800 w, 672 w, 768 w, 525 w, 490 w, 492 w, hex 03 90 54 e3 pll, 04 10 97 00 pll, decimal
+ 640 w, 480 w, 800 w, 672 w, 768 w, 525 w, 490 w, 492 w, hex 85 90 8c e3 pll, 04 10 97 00 pll, decimal
\ Standard timings according to http://www.epanorama.net/documents/pc/vga_timing.html:
\ 640(width)+8(border)=648(hblank) 648(hblank)+8(frontporch)=656(hsync)
@@ -311,10 +291,6 @@
00 0f crt! \ Cursor loc (text mode)
mode-3? mode-12? or if 60 else 00 then f0 11 crt-mask \ Refreshes per line, disable vert intr
mode-12? if 63 else 23 then 17 crt! \ address wrap, sequential access, not CGA compat mode
-
-\ 04 0e crt! \ Make the register dump match the snapshots
-\ 60 0f crt!
-\ 01 49 crt!
;
: general-init ( -- )
@@ -326,9 +302,6 @@
38 40 seq! \ ECK freq
30 4d seq! \ preempt arbiter
08 30 crt! \ DAC speed enhancement
-\ 00 38 crt! \ Signature 0 - not writable, empirically
-\ 21 39 crt! \ Signature 1
-\ 32 3a crt! \ Signature 2
01 3b crt! \ Scratch 2
08 3c crt! \ Scratch 3
c0 f7 crt! \ Spread spectrum
@@ -522,15 +495,10 @@
miscval misc!
-\ 0 0 seq! \ Sequence registers
-
-\ 01 df 01 seq-mask
-\ 00 03 seq!
-
depth bpp1!
- 28 fd 1a seq-mask \ Extended mode memory access (value is 20 in modes 3 and 12)
-
+ 08 cd 1a seq-mask \ Extended mode memory access (unnecessary but okay for modes 3 and 12)
+
init-grf-regs
init-attr-regs
@@ -1289,705 +1257,3 @@
\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
\
\ LICENSE_END
-0 [if]
-Mode 3
-ok .dpy
-ATR 0 1 2 3 4 5 14 7 38 39 3a 3b 3c 3d 3e 3f c 0 f 8 0
-SEQ 3 0 3 0 2
-GRF 0 0 0 0 0 10 e 0 ff
- 0 1 2 3 4 5 6 7 8 9 a b c d e f vtotal1:449 vdisplay1:400 vblank1:407 vblankend1:442
-C00 5f 4f 50 82 55 81 bf 1f 0 4f d e 0 0 1 40 htotal1:800 hdisplay1:640 hblank1:648 hblend1:280?? hsync:680,776
-C10 9c 6e 8f 28 1f 96 b9 a3 ff hfetch1: hoffset1: 28=>320 vsync: 19c = 413 vsyncend1: 415
-C30 8 0 11 0 0 0 1 34 d3 19 e7 2 8 64 20 b
-C40 0 0 0 90 0 0 0 2 0
-C50 d7 af af d7 24 c4 b6 be 8f 83 83 8f 9b 1b 84 6e htotal2: 1240
- hfetch2: 836 hoffset2: 808 htotals: 57=>736 - this matches the vck/lcdck ratio WRT htotal2 of 1240
-C60 ce 72 0 0 0 a2 65 0 f0 0 48 e 0 57 5b 8e !! CR6b[3] simultaneous mode, [2] IGA2 off secondary_dpy_off
- (6a:80) hblankends: 5b=>736
-C70 83 33 83 8f 33 85 3f 22 c7 6b 1 2 3 4 7 a hscale: 0t2184 (639*4096/1199)
- 60
-C80 d 13 16 19 1c 1d 1e 1f e1 0 1 5d 2b 0 b5 1
-C90 10 1f 0 0 8 11 0 10 0 0 0 1b 0 0 0 0
-CA0 0 0 c8 0 8 c3 f9 8b 1 0 0 0 0 0 0 0
-CD0 0 0 2b 0 c0 0 0 0 0 0 0 0 0 0 0 0
-CE0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- d
-CF0 0 0 0 92 0 0 0 c0 0 a 0 0 0
-S10 1 78 8 0 0 0 4c 1f 4e 7f 0 f0 54 0 31 hfetch1: 54 => 1280 secondary_dpy_clk is on (rx1b)
-S20 0 18 14 3d c 0 0 ff ff
-S30 0 6 11 1d c 20 ff
-
- vck: 33.827 ratio of vck to lcdck is 59%, whereas scale factor percent is 53%
- eck: 250.568
-lcdck: 56.914
- vck..... eck..... lcdck...
-S40 38 40 30 ff 97 10 4 69 84 3 9f 8c 5 30 0 5f
-S50 1f 0 0 ff 0 0 ff 0 6 df 0 51 21 f0 0 0
-S60 0 0 0 40 20 d 20 20 80 20 0 0 0 80 1 0
-S70 20 0 f 0 1f 1f 0 0 86 8 10 0 c8 0 0 0
-SA8 0 0 80 80 0 0 0 0
-G20 0 0 0
-
-ok 12 set-vesa-mode mode 12 640x480x4
-ok .dpy
-ATR 0 1 2 3 4 5 14 7 38 39 3a 3b 3c 3d 3e 3f 1 0 f 0 0
-SEQ 3 1 f 0 6
-GRF 0 0 0 0 0 0 5 f ff
- 0 1 2 3 4 5 6 7 8 9 a b c d e f vtotal:525 vdisplay1:480 vblank1:488 vblankend:517
-C00 5f 4f 50 82 54 80 b 3e 0 40 0 0 0 0 0 0 htotal1:800 hdisplay1:640 hblank1:648 hblend:280?? hsync:672,768
-C10 ea 6c df 28 0 e7 4 e3 ff hfetch1: hoffset1: 28=>320 vsync1: 1ea = 491 vsyncend1: 493
-C30 8 0 11 0 0 0 1 34 d3 3c e6 2 8 64 20 b
-C40 0 0 0 90 0 0 0 2 0
-C50 d7 af af d7 24 c4 b6 be 8f 83 83 8f 9b 1b 84 6e htotal2: 1240
- hfetch2: 836 hoffset2: 808 htotals: 57=>736 - this matches the vck/lcdck ratio WRT htotal2 of 1240
-C60 5c 72 0 0 0 a2 65 0 f0 0 48 e 0 57 5b 8e !! CR6b[3] simultaneous mode, [2] IGA2 off secondary_dpy_off
- (6a:80) hblankends: 5b=>736
-C70 83 33 83 8f 33 85 3f 22 22 ab 1 2 3 4 7 a hscale: 0t2184 (639*4096/1199)
-C80 d 13 16 19 1c 1d 1e 1f e1 0 1 5d 2b 0 b5 1
-C90 10 1f 0 0 8 11 0 10 0 0 0 1b 0 0 0 0
-CA0 0 0 c8 0 8 c3 f9 8b 1 0 0 0 0 0 0 0
-CD0 0 0 2b 0 c0 0 0 0 0 0 0 0 0 0 0 0
-CE0 0 0 0 0 0 0 0 0 40 0 0 0 0 0 0 0
-CF0 0 0 0 92 0 0 0 c0 0 a 0 0 0
-S10 1 78 c 0 0 0 4c 1f 4e 7f 0 f0 54 0 31 hfetch1: 54 => 1280
-S20 0 18 14 3d c 0 0 ff ff
-S30 0 6 11 1d 4 20 ff
-S40 38 40 30 ff 97 10 4 69 84 3 9f 8c 5 30 0 5f
-S50 1f 0 0 ff 0 0 ff 0 6 df 0 51 21 f0 0 0
-S60 0 0 0 40 20 d 20 20 80 20 0 0 0 80 1 0
-S70 20 0 f 0 1f 1f 0 0 86 8 10 0 c8 0 0 0
-SA8 0 0 80 80 0 0 0 0
-G20 0 0 0
-ok
-
---- Attempted mode 12 --------
-ATR 0 1 2 3 4 5 14 7 38 39 3a 3b 3c 3d 3e 3f 1 0 f 0 0
-SEQ 3 1 f 0 6
-GRF 0 0 0 0 0 0 5 f ff
- 0 1 2 3 4 5 6 7 8 9 a b c d e f
-C00 5f 4f 50 82 54 80 b 3e 0 40 0 0 0 0 0 0
-C10 ea 6c df 28 0 e7 4 e3 ff
-C30 8 0 11 20 0 10 1 34 fd 96 ff 1 8 74 0 0
-C40 0 0 0 80 0 0 0 2 0
- cf 87
-C50 d7 af af d7 24 44 b5 bd 8f 83 83 8f 9b 1b 88 6a
- 10
-C60 34 51 0 0 0 a2 65 50 f0 0 48 8 0 57 5b 8e
- 87
-C70 83 33 83 8f bb 89 3b 21 21 af 1 2 3 4 7 a
-C80 d 13 16 19 1c 1d 1e 1f 60 0 1 ca ca ca ca 11
-C90 11 0 0 0 8 11 0 10 0 0 0 1b 0 0 0 2
-CA0 0 0 c8 0 3 0 0 8b 1 0 0 0 0 0 0 0
-CD0 0 0 c8 0 0 0 0 0 0 0 0 0 0 0 0 0
-CE0 0 0 0 0 0 0 0 0 40 0 0 0 0 0 0 0
-CF0 0 0 0 80 0 0 0 c0 0 a 0 d 0
-S10 1 78 0 0 0 0 4c 1f 4e 7f 38 f0 54 0 31
-S20 0 18 14 3d c 0 0 ff ff
-S30 c 6 11 1d 4 20 ff
- 40 30
-S40 38 b0 10 ff 97 10 4 79 88 4 9f c 5 30 0 5f
-S50 1f 81 0 ff 0 0 ff 0 8 df 0 51 21 0 0 0
-S60 0 0 0 0 20 0 20 20 e0 20 0 0 0 e0 1 0
- 0 0
-S70 20 4 f 33 1f 1f 0 0 e0 8 10 0 c8 0 0 0
-SA8 0 0 80 80 0 0 0 0
-G20 0 0 0
---- botched mode 12 ---
-ATR 0 1 2 3 4 5 14 7 38 39 3a 3b 3c 3d 3e 3f 1 0 f 0 0
-SEQ 3 1 f 0 6
-GRF 0 0 0 0 0 0 5 f ff
- 0 1 2 3 4 5 6 7 8 9 a b c d e f
-C00 5f 4f 50 82 54 80 b 3e 0 40 0 0 0 0 0 0
-C10 ea 6c df 28 0 e7 4 e3 ff
-C30 8 0 11 20 0 10 1 34 7d 96 ef 1 8 74 0 0
-C40 0 0 0 80 0 0 0 2 0
-C50 d7 af af cf 24 c4 b6 be 8f 83 83 87 9b 1b 88 6a
-C60 a9 51 0 0 0 a2 65 10 f0 0 48 8 0 57 5b 8e
-C70 83 33 83 87 b3 89 3b 21 21 af 1 2 3 4 7 a
-C80 d 13 16 19 1c 1d 1e 1f 60 0 1 ca ca ca ca 11
-C90 11 0 0 0 8 11 0 10 0 0 0 1b 0 0 0 2
-CA0 0 0 c8 0 3 0 0 8b 1 0 0 0 0 0 0 0
-CD0 0 0 c8 0 0 0 0 0 0 0 0 0 0 0 0 0
-CE0 0 0 0 0 0 0 0 0 40 0 0 0 0 0 0 0
-CF0 0 0 0 80 0 0 0 c0 0 a 0 d 0
-S10 1 78 0 0 0 0 4c 1f 4e 7f 8 f0 54 0 31
-S20 0 18 14 3d c 0 0 ff ff
-S30 c 6 11 1d 4 20 ff
-S40 38 40 30 ff 97 10 4 79 88 4 9f c 5 30 0 5f
-S50 1f 81 0 ff 0 0 ff 0 8 df 0 51 21 0 0 0
-S60 0 0 0 0 20 0 20 20 e0 20 0 0 0 e0 1 0
-S70 20 0 f 0 1f 1f 0 0 e0 8 10 0 c8 0 0 0
-SA8 0 0 80 80 0 0 0 0
-G20 0 0 0
-
-----------------
-
-Mode 112 - 640x480x8
-ok 112 set-linear-mode
-ok .dpy
-ATR 0 1 2 3 4 5 14 7 38 39 3a 3b 3c 3d 3e 3f 1 0 f 0 0
-SEQ 3 1 f 0 e
-GRF 0 0 0 0 0 0 5 f ff
- 0 1 2 3 4 5 6 7 8 9 a b c d e f
-C00 5f 4f 4f 83 52 9e b 3e 0 40 0 0 0 0 0 0
-C10 e9 1b df 50 0 df c e3 ff
-C30 8 0 11 26 0 10 1 34 d3 3c e6 2 8 64 20 b
-C40 0 0 0 90 0 0 0 0 0
-C50 d7 af af d7 24 c4 b6 be 8f 83 83 8f 9b 1b 84 6e
-C60 69 72 0 0 0 a0 40 c1 f0 0 c8 0 0 57 5b 8e
-C70 83 33 83 8f 33 85 3f 22 22 ab 1 2 3 4 7 a
-C80 d 13 16 19 1c 1d 1e 1f e1 0 1 5d 2b 0 b5 1
-C90 10 1f 0 0 8 11 0 10 0 0 0 1b 0 0 0 0
-CA0 0 0 c8 0 8 c3 f9 8b 1 0 0 0 0 0 0 0
-CD0 0 0 2b 0 c0 0 0 0 0 0 0 0 0 0 0 0
-CE0 0 0 0 0 0 0 0 0 40 0 0 0 0 0 0 0
-CF0 0 0 0 92 0 0 0 c0 0 a 0 d 0
-S10 1 78 c 0 0 22 4c 1f 4e 7f 8 f0 2c 0 31
-S20 0 18 14 3d c 0 0 ff ff
-S30 0 6 11 1d c 20 ff
-S40 38 40 30 ff 8d 10 5 69 84 3 9f 8c 5 30 0 5f
-S50 1f 0 0 ff 0 0 ff 0 8 5f 0 51 21 f0 0 0
-S60 0 0 0 40 20 d 20 20 80 20 0 0 0 80 1 0
-S70 20 0 f 0 1f 1f 0 0 86 8 10 0 c8 0 0 0
-SA8 0 0 80 80 0 0 0 0
-G20 0 0 0
-ok
-
-
-Mode 115 - 800x600x32
-ok .dpy
-ATR 0 1 2 3 4 5 14 7 38 39 3a 3b 3c 3d 3e 3f 1 0 f 0 0
-SEQ 3 1 f 0 e
-GRF 0 0 0 0 0 0 5 f ff
- 0 1 2 3 4 5 6 7 8 9 a b c d e f
-C00 5f 4f 4f 83 52 9e b 3e 0 40 d e 0 0 1 40
-C10 e9 1b df 50 1f df c a3 ff
-C30 8 0 11 26 0 10 1 34 d3 19 e7 2 8 64 20 b
-C40 0 0 0 90 0 0 0 0 0
-C50 d7 af af d7 24 c4 b6 be 8f 83 83 8f 9b 1b 84 6e vtotal2,s 912 vdisplay2,s 900 vblank2,s 900 vblankend2,s 912
-C60 4a 71 0 0 0 c8 90 c1 f0 0 c8 0 0 57 5b 8e htotals 736 hblankends 736 - probably not used in this mode
-C70 83 33 83 8f 33 85 3f aa ab a3 1 2 3 4 7 a vsync2,s 900 hfetch2
-C80 d 13 16 19 1c 1d 1e 1f e1 0 1 5d 2b 0 b5 1
-C90 10 1f 0 0 8 11 0 10 0 0 0 1b 0 0 0 2
-CA0 0 0 c8 0 8 c3 f9 8b 1 0 0 0 0 0 0 0
-CD0 0 0 2b 0 c0 0 0 0 0 0 0 0 0 0 0 0
-CE0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-CF0 0 0 0 92 0 0 0 c0 0 a 0 d 0
-S10 1 78 8 0 0 22 4c 1f 4e 7f 8 f0 2c 0 31
-S20 0 18 14 3d c 0 0 ff ff
-S30 0 6 11 1d c 20 ff
-vck: 25.236
- vck..... eck..... lcdck...
-S40 38 40 30 ff 8d 10 5 69 84 3 9f 8c 5 30 0 5f
-S50 1f 0 0 ff 0 0 ff 0 8 5f 0 51 21 f0 0 0
-S60 0 0 0 40 20 d 20 20 80 20 0 0 0 80 1 0
-S70 20 0 f 0 1f 1f 0 0 86 8 10 0 c8 0 0 0
-SA8 0 0 80 80 0 0 0 0
-G20 0 0 0
-
-Mode 118 - 1024x768x32
-
-ok .dpy
-N: ATR 3a 38 38 3c 38 3a 39 39 38 3c 3b 3c 3e 3a 38 3c 38 b9 38 d 8
-P: ATR 0 1 2 3 4 5 6 7 8 9 a b c d e f 1 0 f 0 0
- ATR 0 1 2 3 4 5 14 7 38 39 3a 3b 3c 3d 3e 3f 1 0 f 0 0
-
-N: SEQ 0 0 0 0 0
-P: SEQ (same as phx)
- SEQ 3 1 f 0 e
-
-N:GRF 0 0 0
-P:GRF (same as phx)
- GRF 0 0 0 0 0 0 5 f ff
-
- 0 1 2 3 4 5 6 7 8 9 a b c d e f
-
-NC00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-PC00 a3 7f 7f 87 83 94 24 f5 0 60 d e 0 0 4 60
-C00 5f 4f 4f 83 52 9e b 3e 0 40 d e 0 0 1 40
-
-NC10 0 0 0 0 0 0 0 80 0
-PC10 2 18 ff 0 ff 25
-C10 e9 1b df 50 1f df c a3 ff
- signatur scratchpadreg
-NC30 0 0 10 0 0 0 1 34 6d 2e 77 0 0 74 0 0
-PC30 6 30 6d 2e 77 1 74 0 0
-C30 8 0 11 26 0 10 1 34 d3 19 e7 2 8 64 20 b
-
-NC40 80 (RO bits)
-PC40 80 (RO bits)
-C40 0 0 0 90 0 0 0 0 0
-
-Phoenix moves the Hsync -2 (1206 vs 1208) and the Vsync -5 (900 vs 905)
- Hsync,Hsyncend Vsync
-N: b8 c0 89 (syncs)
-P: b8 c0 89 (syncs)
-C50 d7 af af d7 24 c4 b6 be 8f 83 83 8f 9b 1b 84 6e
- 4 8 c
- offset phx: 0200 (1024*Bpp/8) N: 012c (1200*Bpp/8)
- qcount phx: 0100 (1024*Bpp/16) N: 0096 (1200*Bpp/8)
- modetiming iga2en shadow..
-NC60 RO RO 96 2c 41 fa aa 5a
-PC60 0 10 0 0 0 96 2c 41 8 fa aa 5a
-C60 d 70 0 0 0 0 0 c6 f0 0 c8 0 0 57 5b 8e
-
- shadow.............. scale... sclparams.......
-NC70 ab 2a eb ea fa ab 3a 0 3f 38 f b f a a 1d
-PC70 ab 2a eb ea fa ab 3a 0 3f 38 f b f a a 1d
-C70 83 33 83 8f 33 85 3f 69 6a f3 1 2 3 4 7 a
-
- ....................... pnl pwrsequence...
-NC80 1b e b a 1b e 1a b 60 0 1 ca ca ca ca 11
-PC80 1b e b a 1b e 1a b 60 0 1 ca ca ca ca 11
-C80 d 13 16 19 1c 1d 1e 1f e1 0 1 5d 2b 0 b5 1
-
- .. di hscl
-NC90 11 0 0 0 8 11 0 10 0 0 0 1b 0 0 0 0
-PC90 11 0 0 0 8 11 0 10 0 0 0 1b 0 0 0 0
-C90 10 1f 0 0 8 11 0 10 0 0 0 1b 0 0 0 3
-
- scl scl......
-NCA0 0 0 0 0 3 0 0 8b 1 0 0 0 0 0 0 0
-PCA0 0 0 0 0 3 0 0 8b 1 0 0 0 0 0 0 0
-CA0 0 0 c8 0 8 c3 f9 8b 1 0 0 0 0 0 0 0
-
- none of these bits seem to have an effect
- LVDS 2nd chnl output format - sequential, 18 bits (no effect?)
-NCD0 0 0 c8 0 0 0 0 0 0 0 0 0 0 0 0 0
-PCD0 0 0 b 0 c0 0 0 0 0 0 0 0 0 0 0 0
-CD0 0 0 2b 0 c0 0 0 0 0 0 0 0 0 0 0 0
-
-CE0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-
- snapshot spread-spectrum
-NCF0 0 0 0 80 0 0 0 0 0 a 0 d 0
-PCF0 0 0 0 80 0 0 0 c0 0 a 0 d 0
-CF0 0 0 0 92 0 0 0 c0 0 a 0 d 0
-
- FIFO
- Fifodepth mode DVP1_power,ROCECKon
- threshold ext_mem_acc(8),dvi(30)
- wraparound(20),ext_disp_mode_ena(2)!
-NS10 0 40 0 0 30 0
-PS10 36 30 7f 60 60 7f 8 f0 84 (F0 is RO, )
-S10 1 78 8 0 0 22 4c 1f 4e 7f 8 f0 2c 0 31 rr
-
- queuing.
-NS20 4 e 0
-PS20 10
-S20 0 18 14 3d c 0 0 ff ff
-
-PS30 4 ( SR3d - VGIO4 pin status )
-S30 0 6 11 1d c 20 ff
-
- vck: phx: 25.236 p: 65.148 n: 25.056
- eck: phx: 250.568 (not best) N,p: 108.818
-lcdck: phx: 56.914 PM 55 N,p: 56.199 PM 55
-
- arbiter
- arbiter vck....! eck....! lcdck..! arbiter
- 1/8ECKinIdle
-NS40 0 b0 10 54 90 3 79 88 4 9d c 5 8
-PS40 b0 10 b6 c 79 88 4 9d c 5
-
- vck..... eck..... lcdck...
-S40 38 40 30 ff 8d 10 5 69 84 3 9f 8c 5 30 0 5f
-
- NB-fifo-enable iga1-ena timer
- arbiter gfx-nm pcpc dynamic clock
-NS50 3f 0 df 0
-PS50 81 df 0
-S50 1f 0 0 ff 0 0 ff 0 8 5f 0 51 21 f0 0 0
-
- FBsize
- GTI.. GTI
- i2c dvp_drive_strength FBbbase
-NS60 0 0 c8 c8 e0 c8 e0 0
-PS60 0 e0 e0 0
-S60 0 0 0 40 20 d 20 20 80 20 0 0 0 80 1 0
-
- gti..
- arb........ IGA1_hsync(60),clk/1024(6)!
-NS70 c8 4 1d 33 e0 c8 c8
-PS70 4 33 e0
-S70 20 0 f 0 1f 1f 0 0 86 8 10 0 c8 0 0 0
-
-SA8 0 0 80 80 0 0 0 0
-G20 0 0 0
-
-ok .dpy
-
-1280x1024 Mode 11b
-
-ATR 0 1 2 3 4 5 14 7 38 39 3a 3b 3c 3d 3e 3f 1 0 f 0 0
-SEQ 3 1 f 0 e
-GRF 0 0 0 0 0 0 5 f ff
- 0 1 2 3 4 5 6 7 8 9 a b c d e f
-C00 5f 4f 4f 83 52 9e b 3e 0 40 d e 0 0 1 40
-C10 e9 1b df 50 1f df c a3 ff
-C30 8 0 11 26 0 10 1 34 d3 19 e7 2 8 64 20 b
-C40 0 0 0 90 0 0 0 0 0
-C50 d7 af af d7 24 c4 b6 be 8f 83 83 8f 9b 1b 84 6e
-C60 8e 71 0 0 0 2c 80 c6 f0 0 c8 0 0 57 5b 8e
-C70 83 33 83 8f 33 85 3f 69 6a f0 1 2 3 4 7 a
-C80 d 13 16 19 1c 1d 1e 1f e1 0 1 5d 2b 0 b5 1
-C90 10 1f 0 0 8 11 0 10 0 0 0 1b 0 0 0 3
-CA0 0 0 0 0 8 c3 f9 8b 1 0 0 0 0 0 0 0
-CD0 0 0 2b 0 c0 0 0 0 0 0 0 0 0 0 0 0
-CE0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-CF0 0 0 0 92 0 0 0 c0 0 a 0 d 0
-S10 1 78 8 0 0 22 4c 1f 4e 7f 8 f0 2c 0 31
-S20 0 18 14 3d c 0 0 ff ff
-S30 0 6 11 1d 4 20 ff
-
-vck: 25.236
- vck..... eck..... lcdck...
-S40 38 40 30 ff 8d 10 5 69 84 3 9f 8c 5 30 0 5f
-S50 1f 0 0 ff 0 0 ff 0 8 5f 0 51 21 f0 0 0
-S60 0 0 0 40 20 d 20 20 80 20 0 0 0 80 1 0
-S70 20 0 f 0 1f 1f 0 0 86 8 10 0 c8 0 0 0
-SA8 0 0 80 80 0 0 0 0
-G20 0 0 0
-
- Native 1200x900 LCD only
-
-ok .dpy
-ATR 3a 38 38 3c 38 3a 39 39 38 3c 3b 3c 3e 3a 38 3c 38 b9 38 d 8
-SEQ 0 0 0 0 0
-GRF 0 0 0 0 0 0 0 0 0
- 0 1 2 3 4 5 6 7 8 9 a b c d e f
-C00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-C10 0 0 0 0 0 0 0 80 0
-C30 0 0 10 0 0 0 1 34 6d 2e 77 0 0 74 0 0
-C40 0 0 0 80 0 0 0 0 0
-C50 d7 af af d7 24 c4 b8 c0 8f 83 83 8f 9b 1b 89 6e
-C60 ae 51 0 0 0 96 2c 41 f0 0 c8 0 0 fa aa 5a
-C70 ab 2a eb ea fa ab 3a 0 3f 38 f b f a a 1d
-C80 1b e b a 1b e 1a b 60 0 1 ca ca ca ca 11
-C90 11 0 0 0 8 11 0 10 0 0 0 1b 0 0 0 0
-CA0 0 0 0 0 3 0 0 8b 1 0 0 0 0 0 0 0
-CD0 0 0 c8 0 0 0 0 0 0 0 0 0 0 0 0 0
-CE0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-CF0 0 0 0 80 0 0 0 0 0 a 0 d 0
-S10 1 78 8 0 0 0 40 0 0 7f 30 f0 0 0 31
-S20 4 e 0 3d c 0 0 ff ff
-S30 0 6 11 1d c 20 ff
-S40 0 b0 10 ff 54 90 3 79 88 4 9d c 5 8 0 5f
-S50 3f 0 0 ff 0 0 ff 0 0 df 0 51 21 0 0 0
-S60 0 0 0 0 20 0 c8 c8 e0 c8 0 0 0 e0 0 0
-S70 c8 4 1d 33 1f 1f 0 0 e0 c8 c8 0 c8 0 0 0
-SA8 0 0 80 80 0 0 0 0
-G20 0 0 0
-
-\ After d# 1024 d# 768 d# 16 set-resolution width height init-primary-mode
-\ "P" case
-ok .dpy
-ATR 0 1 2 3 4 5 6 7 8 9 a b c d e f 1 0 f 0 0
-SEQ 3 1 f 0 e
-GRF 0 0 0 0 0 0 5 f ff
- 0 1 2 3 4 5 6 7 8 9 a b c d e f
-C00 a3 7f 7f 87 83 94 24 f5 0 60 d e 0 0 4 60
-C10 2 18 ff 0 1f ff 25 a3 ff
-C30 8 0 11 6 0 30 1 34 6d 2e 77 1 8 74 0 0
-C40 0 0 0 80 0 0 0 0 0
-C50 d7 af af d7 24 c4 b8 c0 8f 83 83 8f 9b 1b 89 6e
-C60 0 10 0 0 0 96 2c 41 f0 0 8 0 0 fa aa 5a
-C70 ab 2a eb ea fa ab 3a 0 3f 38 f b f a a 1d
-C80 1b e b a 1b e 1a b 60 0 1 ca ca ca ca 11
-C90 11 0 0 0 8 11 0 10 0 0 0 1b 0 0 0 0
-CA0 0 0 0 0 3 0 0 8b 1 0 0 0 0 0 0 0
-CD0 0 0 b 0 c0 0 0 0 0 0 0 0 0 0 0 0
-CE0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-CF0 0 0 0 80 0 0 0 c0 0 a 0 d 0
-S10 1 78 8 0 0 36 60 7f 60 7f 8 f0 84 0 31
-S20 0 18 10 3d c 0 0 ff ff
-S30 0 6 11 1d 4 20 ff
-S40 38 b0 10 ff b6 c 5 79 88 4 9d c 5 30 0 5f
-S50 1f 81 0 ff 0 0 ff 0 8 df 0 51 21 0 0 0
-S60 0 0 0 0 20 d 20 20 e0 20 0 0 0 e0 0 0
-S70 20 4 f 33 1f 1f 0 0 e0 8 10 0 c8 0 0 0
-SA8 0 0 80 80 0 0 0 0
-G20 0 0 0
-
-OFW mode 3 centered
-ok .dpy
-ATR 0 1 2 3 4 5 14 7 38 39 3a 3b 3c 3d 3e 3f c 0 f 8 0
-SEQ 3 0 3 0 2
-GRF 0 0 0 0 0 10 e 0 ff
- 0 1 2 3 4 5 6 7 8 9 a b c d e f
- 1 40 Cursor loc
-C00 5f 4f 50 82 55 81 bf 1f 0 4f d e 0 0 ff ff
- 6e 11: Protect, bandwidth, disable vert intr
-C10 9c 8e 8f 28 1f 96 b9 a3 ff
- 0 0 d3 19 e7 2 64 20 b 33: HSYNC adjust 35: Line compare[10] 38-3f: signature, scratch
-C30 8 0 11 1 0 10 1 34 6d 2e 77 1 8 74 0 0
- 43 is not really RO
- 90 2 43: reserved-RO 47: LCD simultaneous mode backdorr 8/9 dot clks
-C40 0 0 0 80 0 0 0 0 0
-
- Xaf af d7 c4 b6 be 8f 83 83 8f 9b 1b 84 6e IGA2 timing - different because centering
-C50 d7 7f 97 bf db a4 9f a7 8f 8f 89 95 52 b 8e 53
-
- !! !! !! 6b: IGA2 screen on!!! 6d-6e: shadow
- XRO RO 0 a2 65 0 e 57 5b 62: 2 is reserved bit! - not really RO. 65-67: fetch,offset
-C60 c2 52 2 0 0 28 48 40 f0 0 48 8 0 96 9a 8e
-
- 83 33 83 8f 33 85 3f 22 c7 6b 1 2 3 4 7 a 70-76: shadow 77-79: scaling 7a-87: scaling params ...
-C70 8f 13 89 95 aa 8f 24 0 1f 18 f f f e b 1d
-
- d 13 16 19 1c 1d 1e 1f e1 5f 2b b5 1 88: lcd panel type 8b-92: power sequence ctl
-C80 1b e b a 1b f 1e b 60 0 1 ca ca ca ca 11
-
- 10 1f
-C90 11 0 0 0 8 11 0 10 0 0 0 1b 0 0 0 0
-
- c8 8 c3 f9 a2: scaling enable a4: undocumented a5-a6: scaling
-CA0 0 0 0 0 3 0 0 8b 1 0 0 0 0 0 0 0
-
- 2b c0
-CD0 0 0 c8 0 0 0 0 0 0 0 0 0 0 0 0 0 d2: lvds control d4: lvds2 second power sequence
-CE0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 92 0
-CF0 0 0 0 80 0 0 0 c0 0 a 0 d 0 f3: snapshot fb: interlace timing
- 4c 0 16: reserved bit! but important 1a: Which LUT !
-S10 1 78 8 0 0 0 c 1f 4e 7f 1 f0 54 0 31
- 14 22: fifo
-S20 0 18 10 3d c 0 0 ff ff
- c 3d: vgpio4 pin status
-S30 0 6 11 1d 4 20 ff
- 33.827MH 250.568MHz 56.914MH
- 59.198MH 108.281MHz 59.198MH
- 40 30 97 10 4 69 84 3 9f 8c 41-42: arbiter 44-: vck 47-: eck 4a-: lcdck
-S40 38 b0 10 ff 9d c 5 79 88 4 9d c 5 30 0 5f
- 51 f0 5b: RO 5d: timer
-S50 1f 0 0 ff 0 0 ff 0 6 df 0 21 21 0 0 0
- 40 d 80 80 1 64: I2C 66: GTI 68: fbsize 6d-6e: fbbase
-S60 0 0 0 0 20 0 20 20 e0 20 0 0 0 e0 0 0
- 86 78: sync polarity, clock source
-S70 20 0 f 0 1f 1f 0 0 e0 8 10 0 c8 0 0 0
-SA8 0 0 80 80 0 0 0 0
-G20 0 0 0
-
-OFW mode 3 expanded
-ATR 0 1 2 3 4 5 14 7 38 39 3a 3b 3c 3d 3e 3f c 0 f 8 0
-SEQ 3 0 3 0 2
-GRF 0 0 0 0 0 10 e 0 ff
- 0 1 2 3 4 5 6 7 8 9 a b c d e f
-C00 5f 4f 50 82 55 81 bf 1f 0 4f d e 0 0 ff ff 1e,f: cursor lock
- 6e 8f
-C10 9c 8e ff 28 1f 96 b9 a3 ff
- signature....scratch..
-C30 8 0 11 1 0 14 1 34 0 0 0 1 8 74 0 0
- 2 backdoor for 8/9 dot clocks
-C40 0 0 0 90 0 0 0 0 0
- b6 be 84 6e
-C50 d7 af af d7 24 c4 b7 bf 8f 83 83 8f 9b 1b 88 6d
- a2 65 00 57 5b !! 65: fetch 66: offset 67: bpp 6d,e: shadow
-C60 22 52 0 0 0 28 50 40 f0 0 48 e 0 4d 51 8e
- 33r85 3f 22 c7 6b
-C70 83 33 83 8f bb 89 3e 21 c6 67 1 2 3 4 7 a
- 5d 2b 0 b5 1 8b-92: power sequence ctl
-C80 d 13 16 19 1c 1d 1e 1f e1 0 1 ca ca ca ca 11
- 10 1f 0 9f: hscale
-C90 11 0 0 0 8 11 0 10 0 0 0 1b 0 0 0 2
- 8 a4: undocumented
-CA0 0 0 c8 0 3 0 0 8b 1 0 0 0 0 0 0 0
-CD0 0 0 2b 0 c0 0 0 0 0 0 0 0 0 0 0 0
-CE0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 92 f3: snapshot
-CF0 0 0 0 80 0 0 0 c0 0 a 0 0 0
- 4c 0 16: undocumented important bit 1a: DVI sense
-S10 1 78 8 0 0 0 c 1f 4e 7f 30 f0 54 0 31
-S20 0 18 14 3d c 0 0 ff ff
- c 3d: vgpio4 pin status
-S30 0 6 11 1d 4 20 ff
- 40 30 97 10 4 69 84 3 9f 8c 41-42: arbiter 44-: vck 47-: eck 4a-: lcdck
-S40 38 b0 10 ff 9d c 5 79 88 4 9d c 5 30 0 5f
- 51 f0 5b: RO 5d: timer
-S50 1f 0 0 ff 0 0 ff 0 6 df 0 21 21 0 0 0
- 40 d 80 80 1 64: I2C 66: GTI 68: fbsize 6d-6e: fbbase
-S60 0 0 0 0 20 0 20 20 e0 20 0 0 0 e0 0 0
-S70 20 0 f 0 1f 1f 0 0 86 8 10 0 c8 0 0 0
-SA8 0 0 80 80 0 0 0 0
-G20 0 0 0
-
-OFW mode 3 patched
-ok .dpy
-ATR 0 1 2 3 4 5 14 7 38 39 3a 3b 3c 3d 3e 3f c 0 f 8 0
-SEQ 3 0 3 0 2
-GRF 0 0 0 0 0 10 e 0 ff
- 0 1 2 3 4 5 6 7 8 9 a b c d e f
-C00 5f 4f 50 82 55 81 bf 1f 0 4f d e 0 0 ff ff
-C10 9c 6e 8f 28 1f 96 b9 a3 ff
-C30 8 0 11 0 0 0 1 34 0 0 0 1 8 74 0 0
-C40 0 0 0 90 0 0 0 2 0
-C50 d7 af af d7 24 c4 b6 be 8f 83 83 8f 9b 1b 84 6e
-C60 13 50 0 0 0 a2 65 0 f0 0 48 e 0 57 5b 8e
-C70 83 33 83 8f 33 85 3f 22 c7 6b 1 2 3 4 7 a
-C80 d 13 16 19 1c 1d 1e 1f e1 0 1 5d 2b 0 b5 1
- N 2
-C90 10 1f 0 0 8 11 0 10 0 0 0 1b 0 0 0 0
-CA0 0 0 c8 0 8 c3 f9 8b 1 0 0 0 0 0 0 0
-CD0 0 0 2b 0 c0 0 0 0 0 0 0 0 0 0 0 0
-CE0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-CF0 0 0 0 92 0 0 0 c0 0 a 0 0 0
- N9f
-S10 1 78 8 0 0 0 4c 1f 4e 7f 0 f0 54 0 31
-S20 0 18 14 3d c 0 0 ff ff
-S30 0 6 11 1d 4 20 ff
-S40 38 40 30 ff 97 10 4 69 84 3 9f 8c 5 30 0 5f
-S50 1f 0 0 ff 0 0 ff 0 6 df 0 51 21 f0 0 0
- N 0
-S60 0 0 0 40 20 d 20 20 80 20 0 0 0 e0 0 0
-S70 20 0 f 0 1f 1f 0 0 86 8 10 0 c8 0 0 0
-SA8 0 0 80 80 0 0 0 0
-G20 0 0 0
-
- === after last set of changes ---
-ok .dpy
-ATR 0 1 2 3 4 5 14 7 38 39 3a 3b 3c 3d 3e 3f c 0 f 8 0
-SEQ 3 0 3 0 2
-GRF 0 0 0 0 0 10 e 0 ff
- 0 1 2 3 4 5 6 7 8 9 a b c d e f
-
-C00 5f 4f 50 82 52 9e bf 5f 0 4f d e 0 0 4 60
-C00 5f 4f 50 82 55 81 bf 1f 0 4f d e 0 0 ff ff
- 6e
-C10 9c 8e 8f 28 1f 96 b9 a3 ff
- 0 0
-C30 8 0 11 1 0 10 1 34 ed ae 7f 1 8 74 0 0
- 90 2
-C40 0 0 0 80 0 0 0 0 0
- b6 be 84 6e
-C50 d7 af af d7 24 c4 b7 bf 8f 83 83 8f 9b 1b 88 6d
- 0 a2 65 0 e 57 5b
-C60 3e 50 2 0 0 28 50 50 f0 0 48 8 0 4d 51 8e
- 85 3f 22 c7 6b
-C70 83 33 83 8f bb 89 3e 21 c6 67 1 2 3 4 7 a
-C80 d 13 16 19 1c 1d 1e 1f 60 0 1 ca ca ca ca 11
- 0
-C90 11 0 0 0 8 11 0 10 0 0 0 1b 0 0 0 2
- 8 c3 f9
-CA0 0 0 c8 0 3 0 0 8b 1 0 0 0 0 0 0 0
- 2b c0
-CD0 0 0 c8 0 0 0 0 0 0 0 0 0 0 0 0 0
-CE0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 92
-CF0 0 0 0 80 0 0 0 c0 0 a 0 d 0
-S10 1 78 8 0 0 0 4c 1f 4e 7f 0 f0 54 0 31
-S20 0 18 14 3d c 0 0 ff ff
- c
-S30 0 6 11 1d 4 20 ff
-S40 38 40 30 ff 97 10 4 69 84 3 9f 8c 5 30 0 5f
- f0
-S50 1f 0 0 ff 0 0 ff 0 6 df 0 51 21 0 0 0
- 40 d (80 80 1)size
-S60 0 0 0 0 20 0 20 20 e0 20 0 0 0 e0 0 0
- 86
-S70 20 0 f 0 1f 1f 0 0 e0 8 10 0 c8 0 0 0
-SA8 0 0 80 80 0 0 0 0
-G20 0 0 0
-
- \ Working settings:
-ok vtotal1@ .d vdisplay1@ .d vblank1@ .d vblankend1@ .d vsync1@ .d vsyncend1@ .
-449 400 407 186 412 415 [449 400 {400+7} {442=449-7} 412 430]
-ok vtotal2@ .d vdisplay2@ .d vblank2@ .d vblankend2@ .d vsync2@ .d vsyncend2@ .
-912 900 900 912 901 911 [sss sss sss sss 905! 910!]
-ok vtotals@ .d vdisplays@ .d vblanks@ .d vblankends@ .d vsyncs@ .d vsyncends@ .
-912 900 900 912 901 911 [sss sss sss sss 905! 910!]
-ok htotal1@ .d hdisplay1@ .d hblank1@ .d hblankend1@ .d hsync1@ .d hsyncend1@ .
-800 640 648 4120 688 705 [800 640 {640+8} {792 - possibly compute as htotal-8} 680 776]
-ok htotal2@ .d hdisplay2@ .d hblank2@ .d hblankend2@ .d hsync2@ .d hsyncend2@ .
-1240 1200 1200 1240 1207 1215 [sss sss sss sss 1208! 1216!]
-ok htotals@ .d hblankends@ .d
-736 736 [ {htotal2 * vclk/lcdck} {htotal2 * vclk/lcdck} ]
-ok hfetch1@ .d hoffset1@ .d hfetch2@ .d hoffset2@ .d
-16 320 2592 808
-ok bpp1@ .d
-8
-vck pll: 97 10 4 33.8 MHz
-eck pll: 69 84 3
-lcd pll: 9f 8c 5 56.9 MHz
-misc cf
-
- partial recipe:q
-
- fill timing regs per above
- text-mode3
- cf misc!
-
-need simultaneous mode and disable-channel2
-
-[then]
-0 [if]
-
- === Another working setup ===
-ok .timings
-IGA1: 640 648 680 776 1304 800 400 407 413 415 442 449
-IGA2: 1200 1200 1207 1215 1240 1240 900 900 901 911 912 912
-Shad: 736 736 900 900 901 911 912 912
-fetch1: 1280 offset1: 320 fetch2: 2592 offset2: 808 bpp: 8
-VCK: 97 10 4
-ECK: 0 0 0
-LCK: 9f 8c 5
-MISC cf
-
-ok .dpy
-ATR 0 1 2 3 4 5 6 7 8 9 a b c d e f c 0 f 8 0
-SEQ 3 0 3 0 2
-GRF 0 0 0 0 0 10 e 0 ff
- 0 1 2 3 4 5 6 7 8 9 a b c d e f
-C00 5f 4f 50 82 55 81 bf 1f 0 4f d e 0 0 1 40
-C10 9c 6e 8f 28 1f 96 b9 a3 ff
-C30 8 0 11 0 0 0 1 34 ef ee 7f 2 8 64 20 b
-C40 0 0 0 90 0 0 0 2 0
-C50 d7 af af d7 24 c4 b6 be 8f 83 83 8f 9b 1b 84 6e
-C60 5c 72 0 0 0 a2 65 0 f0 0 48 e 0 57 5b 8e
-C70 83 33 83 8f bb 89 3e 21 c6 67 1 2 3 4 7 a
-C80 d 13 16 19 1c 1d 1e 1f 60 0 1 ca ca ca ca 11
-C90 11 0 0 0 8 11 0 10 0 0 0 1b 0 0 0 2
-CA0 0 0 c8 0 3 0 0 8b 1 0 0 0 0 0 0 0
-CD0 0 0 c8 0 0 0 0 0 0 0 0 0 0 0 0 0
-CE0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-CF0 0 0 0 80 0 0 0 c0 0 a 0 d 0
-S10 1 78 8 0 0 0 c 1f 60 7f 0 f0 54 0 31
-S20 0 18 10 3d c 0 0 ff ff
-S30 0 6 11 1d 4 20 ff
-S40 38 40 30 ff 97 10 4 69 84 3 9f 8c 5 30 0 5f
-S50 1f 0 0 ff 0 0 ff 0 8 df 0 21 21 0 0 0
-S60 0 0 0 0 20 0 20 20 e0 20 0 0 0 e0 0 0
-S70 20 0 f 0 1f 1f 0 0 86 8 10 0 c8 0 0 0 <<< the 86 here sometimes works better as e6, lest LCD lose sync
-SA8 0 0 80 80 0 0 0 0
-G20 0 0 0
-
- ECK is irrelevant - zapping it doesn't change the display
-
- I got the above result by running xtext-mode3 then blasting with
-
-" "(5f 4f 50 82 55 81 bf 1f 00 4f 0d 0e 00 00 01 40)" 0 do dup i + c@ 00 i + crt! loop
-" "(9c 6e 8f 28 1f 96 b9 a3 ff)" 0 do dup i + c@ 10 i + crt! loop
-" "(08 00 11 00 00 00 01 34 d3 19 e7 02 08 64 20 0b)" 0 do dup i + c@ 30 i + crt! loop
-" "(00 00 00 90 00 00 00 02 00)" 0 do dup i + c@ 40 i + crt! loop
-" "(d7 af af d7 24 c4 b6 be 8f 83 83 8f 9b 1b 84 6e)" 0 do dup i + c@ 50 i + crt! loop
-" "(ce 72 00 00 00 a2 65 00 f0 00 48 0e 00 57 5b 8e)" 0 do dup i + c@ 60 i + crt! loop
-" "(83 33 83 8f 33 85 3f 22 c7 6b)" 0 do dup i + c@ 70 i + crt! loop
-00 9f crt!
-
- then 00 15 seq!
-
-Problems:
- CR13 40>28 hoffset1
- CR65 28>a2 hfetch2.low
- CR66 50>65 hoffset2 <<<<< IMPORTANT
- CR67 50>00 bpp, IGA2 Extend 10 Bit Mode LSB Selection
-
- SR1c 2c>54 hfetch1
- SR15 22>00 When 22, access to the EGA frame buffer is denied either 20 or 02 or 00 works
-
-9f8c85 => 56.915
-971004 => 37.782 ratio .6638
-
-9d8c85 => 56.199
-a79084 => 37.362 ratio .6648
-
-[then]
Modified: dev/via/unichrome/vgamodes.fth
===================================================================
--- dev/via/unichrome/vgamodes.fth 2009-10-27 16:23:11 UTC (rev 1434)
+++ dev/via/unichrome/vgamodes.fth 2009-10-27 20:13:52 UTC (rev 1435)
@@ -73,6 +73,7 @@
d# 640 d# 400 8 set-resolution
set-primary-mode
expanded
+ 3 note-mode
;
: graphics-mode12 ( -- )
olpc-crt-on \ Restore power to IGA1, as we need it for VGA modes
@@ -80,11 +81,12 @@
d# 640 d# 480 4 set-resolution
set-primary-mode
expanded
+ h# 12 note-mode
;
warning !
-: 640x480x32 ( -- ) olpc-lcd-mode d# 640 d# 480 d# 32 change-resolution ; \ VESA mode 112
-: 800x600x32 ( -- ) olpc-lcd-mode d# 800 d# 600 d# 32 change-resolution ; \ VESA mode 115
-: 1024x768x32 ( -- ) olpc-lcd-mode d# 1024 d# 768 d# 32 change-resolution ; \ VESA mode 118
-: 1200x900x16 ( -- ) olpc-lcd-mode d# 1024 d# 768 d# 16 change-resolution ;
-: 1200x900x32 ( -- ) olpc-lcd-mode d# 1024 d# 768 d# 32 change-resolution ;
+: 640x480x32 ( -- ) olpc-lcd-mode d# 640 d# 480 d# 32 change-resolution h# 112 note-mode ; \ VESA mode 112
+: 800x600x32 ( -- ) olpc-lcd-mode d# 800 d# 600 d# 32 change-resolution h# 115 note-mode ; \ VESA mode 115
+: 1024x768x32 ( -- ) olpc-lcd-mode d# 1024 d# 768 d# 32 change-resolution h# 118 note-mode ; \ VESA mode 118
+: 1200x900x16 ( -- ) olpc-lcd-mode d# 1024 d# 768 d# 16 change-resolution note-native-mode ;
+: 1200x900x32 ( -- ) olpc-lcd-mode d# 1024 d# 768 d# 32 change-resolution native-mode# 1- note-mode ;
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