[openfirmware] r1410 - cpu/x86/pc/olpc/via
svn at openfirmware.info
svn at openfirmware.info
Sat Oct 10 01:36:04 CEST 2009
Author: wmb
Date: 2009-10-10 01:36:03 +0200 (Sat, 10 Oct 2009)
New Revision: 1410
Modified:
cpu/x86/pc/olpc/via/ioinit.fth
Log:
Via - A couple of startup register tweaks suggested by Via.
Modified: cpu/x86/pc/olpc/via/ioinit.fth
===================================================================
--- cpu/x86/pc/olpc/via/ioinit.fth 2009-10-09 20:23:36 UTC (rev 1409)
+++ cpu/x86/pc/olpc/via/ioinit.fth 2009-10-09 23:36:03 UTC (rev 1410)
@@ -116,6 +116,7 @@
[then]
d# 16 4 devfunc \ EHCI
+ 41 20 20 mreg \ Evaluate PERIODIC Enable bit only at beginning of micro-frame 0 (undocumented)
42 40 40 mreg \ Enable Check PRESOF of ITDOUT Transaction during Fetching Data from DRAM
43 c0 c0 mreg \ Enable Dynamic Clock Scheme - 66MHz (80) & 33MHz (40)
48 20 00 mreg \ Disable DMA bursts
@@ -233,6 +234,7 @@
9f ff ad mreg \ be like Phx (slot 3 is Card Reader not SDIO)
[then]
+ b0 08 00 mreg \ The BIOS Porting Note says to clear this bit. Phoenix and coreboot agree.
b4 80 00 mreg \ No positive decoding for UART1 ???
b7 40 40 mreg \ 40 res be like Phx
uart-dma-io-base wbsplit swap ( bits15:8 bits7:0 )
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