[openfirmware] r1388 - cpu/x86/pc/olpc/via
svn at openfirmware.info
svn at openfirmware.info
Sat Oct 3 00:03:37 CEST 2009
Author: wmb
Date: 2009-10-03 00:03:37 +0200 (Sat, 03 Oct 2009)
New Revision: 1388
Modified:
cpu/x86/pc/olpc/via/addrs.fth
cpu/x86/pc/olpc/via/demodram.fth
cpu/x86/pc/olpc/via/dramtiming.fth
cpu/x86/pc/olpc/via/probemem.fth
cpu/x86/pc/olpc/via/romreset.bth
cpu/x86/pc/olpc/via/startgfxinit.fth
cpu/x86/pc/olpc/via/starthostctl.fth
Log:
Via - support 32-bit memory width controlled by memory ID1 jumper.
Modified: cpu/x86/pc/olpc/via/addrs.fth
===================================================================
--- cpu/x86/pc/olpc/via/addrs.fth 2009-10-02 22:00:49 UTC (rev 1387)
+++ cpu/x86/pc/olpc/via/addrs.fth 2009-10-02 22:03:37 UTC (rev 1388)
@@ -19,7 +19,8 @@
dropin-base h# 20 + constant ResetBase \ Location of "reset" dropin in ROM
-h# 3b00.0000 value fw-pa \ Changed in probemem.fth
+0 value fw-pa \ Set in probemem.fth
+\ h# 3b00.0000 value fw-pa \ Changed in probemem.fth
\ h# 3bc0.0000 value fw-pa \ Changed in probemem.fth
\ h# 1bc0.0000 value fw-pa \ Changed in probemem.fth
\ h# bc0.0000 value fw-pa \ Changed in probemem.fth
@@ -38,7 +39,8 @@
h# 40.0000 constant /dma-extra \ In case the firmware region isn't enough
/fw-ram /dma-extra + constant dma-size \ We let the DMA area overlap the FW area
-fw-pa /dma-extra - constant dma-base
+\ fw-pa /dma-extra - constant dma-base
+0 value dma-base \ Set in probemem.fth
h# f.0000 constant suspend-base \ In the DOS hole
h# f.0008 constant resume-entry
Modified: cpu/x86/pc/olpc/via/demodram.fth
===================================================================
--- cpu/x86/pc/olpc/via/demodram.fth 2009-10-02 22:00:49 UTC (rev 1387)
+++ cpu/x86/pc/olpc/via/demodram.fth 2009-10-02 22:03:37 UTC (rev 1388)
@@ -375,7 +375,9 @@
56 ff 00 mreg \ Rank map B ?
57 ff 00 mreg \ Rank map B ?
+ end-table
+ 0 3 devfunc
40 ff rank-top0 mreg \ Rank top 0 (register value in units of 64MB)
41 ff rank-top1 mreg \ Rank top 1
42 ff rank-top2 mreg \ Rank top 2
@@ -387,17 +389,20 @@
4b ff rank-base3 mreg \ Rank base 3
end-table
- h# 15 port80
+ acpi-io-base 48 + port-rl h# 1000.0000 # ax and 0<> if \ Memory ID1 bit
+ 0 3 devfunc
+ 6c 20 20 mreg \ Enable 32-bit memory width mode - channel A
+ d4 30 10 mreg \ ODT off for low 32 bits
+ end-table
- total-size 8f60 config-wb \ DRAM Bank 7 ending address - controls DMA upstream
- 0388 config-rb ax bx mov 0385 config-setup bx ax mov al dx out \ Copy Low Top from RO reg 88 to reg 85
- 0388 config-rb ax bx mov 8fe5 config-setup bx ax mov al dx out \ Copy Low Top from RO reg 88 to SB Low Top e5
+ 0388 config-rb ax bx mov 1 # bx shr 0385 config-setup bx ax mov al dx out \ Copy Low Top from RO reg 88 to reg 85
+ else
+ 0388 config-rb ax bx mov 0385 config-setup bx ax mov al dx out \ Copy Low Top from RO reg 88 to reg 85
+ then
-\ d# 17 7 devfunc
-\ e6 ff 07 mreg \ Enable Top, High, and Compatible SMM
-\ end-table
+ h# 15 port80
-1 [if] \ Very simple memtest
+0 [if] \ Very simple memtest
long-offsets on
ax ax xor
h# 12345678 # bx mov \ Data value to write to address 0
@@ -464,7 +469,7 @@
h# 17 port80
-1 [if]
+0 [if]
ax ax xor
h# 12345678 # bx mov
bx 0 [ax] mov
Modified: cpu/x86/pc/olpc/via/dramtiming.fth
===================================================================
--- cpu/x86/pc/olpc/via/dramtiming.fth 2009-10-02 22:00:49 UTC (rev 1387)
+++ cpu/x86/pc/olpc/via/dramtiming.fth 2009-10-02 22:03:37 UTC (rev 1388)
@@ -85,3 +85,12 @@
rank-size #ranks * constant total-size
[then]
+
+h# 400.0000 constant /fbmem
+: >fbmem-base ( size/64M -- low high )
+ d# 26 lshift ( memsize-in-bytes )
+ /fbmem - ( memsize-less-framebuf-size )
+ d# 21 rshift wbsplit ( low high )
+;
+
+: dblfudge32 2/ ;
Modified: cpu/x86/pc/olpc/via/probemem.fth
===================================================================
--- cpu/x86/pc/olpc/via/probemem.fth 2009-10-02 22:00:49 UTC (rev 1387)
+++ cpu/x86/pc/olpc/via/probemem.fth 2009-10-02 22:03:37 UTC (rev 1388)
@@ -5,30 +5,13 @@
0 value total-ram-cached
: total-ram ( -- ramsize )
total-ram-cached ?dup if exit then
- \ Search for the last "top of rank" value
- h# 340 h# 343 do
- i config-b@ ?dup if ( chunks ) \ Each chunk is 64 MiB
- d# 26 lshift ( bytes )
- dup to total-ram-cached
- unloop exit
- then
- -1 +loop
- ." Can't get total RAM size!" cr
- h# 1000.0000
+ h# 385 config-b@ d# 24 lshift
dup to total-ram-cached
;
-\ Offset of frame buffer/display memory within the memory array
-: fb-offset ( -- offset ) mem-info-pa 4 + l@ ;
+\ Excludes RAM assigned to the frame buffer and used by OFW page tables
+: system-ram ( -- offset ) mem-info-pa 4 + l@ ;
-\ Excludes RAM assigned to the frame buffer
-: system-ram ( -- extant avail )
- fb-offset
-;
-
-\ This may require adjustment if we steal additional SMI memory
-: fbsize ( -- ) total-ram fb-offset - ;
-
dev /memory
\ Excludes RAM already used for page tables
Modified: cpu/x86/pc/olpc/via/romreset.bth
===================================================================
--- cpu/x86/pc/olpc/via/romreset.bth 2009-10-02 22:00:49 UTC (rev 1387)
+++ cpu/x86/pc/olpc/via/romreset.bth 2009-10-02 22:03:37 UTC (rev 1388)
@@ -60,8 +60,10 @@
fload ${BP}/cpu/x86/pc/olpc/via/startmacros.fth \ Via-oriented startup macros
fload ${BP}/cpu/x86/pc/olpc/via/dramtiming.fth
+fload ${BP}/cpu/x86/pc/mmxdot.fth
start-assembling
+ResetBase to asm-origin \ Necessary for mmxdot
hex
@@ -72,6 +74,7 @@
fload ${BP}/cpu/x86/pc/romfind.fth \ find-dropin subroutine
[ifdef] debug-startup
+fload ${BP}/cpu/x86/pc/mmxdotcode.fth \ Memoryless numeric output
fload ${BP}/cpu/x86/pc/dot.fth \ Numeric output subroutine
\ fload ${BP}/cpu/x86/pc/olpc/via/startinteract.fth \ emitpause subroutine
[then]
@@ -90,6 +93,10 @@
2 92 port-wb \ Enable A20
\ External A20GATE is disabled automatically because the internal KBC is on by default (cfg reg 8851 bit 0)
+ acpi-io-base 1 + 8888 config-ww \ Set ACPI base address
+\ 88 8881 config-wb \ Enable ACPI regs, 32-bit PM timer, guard RTC against power glitches
+ 8c 8881 config-wb \ Enable ACPI regs, 32-bit PM timer, guard RTC against power glitches
+
fload ${BP}/cpu/x86/pc/olpc/via/startcacheasram.fth
\ cache_as_ram_auto.c: amd64_main()
@@ -105,14 +112,9 @@
\ This needs to be done early so we can test various GPIO bits,
\ including SERIAL_EN
- acpi-io-base 1 + 8888 config-ww \ Set ACPI base address
- 8c 8881 config-wb \ Enable ACPI regs, 32-bit PM timer, guard RTC against power glitches
+\ acpi-io-base 1 + 8888 config-ww \ Set ACPI base address
+\ 8c 8881 config-wb \ Enable ACPI regs, 32-bit PM timer, guard RTC against power glitches
-[ifdef] debug-startup
- cominit #) call
-[then]
-
- char + report
h# 1d port80
\ This is a device ID backdoor to fake out the ID so Ubuntu will install
@@ -120,6 +122,11 @@
fload ${BP}/cpu/x86/pc/olpc/via/starthostctl.fth
+[ifdef] debug-startup
+ cominit #) call
+[then]
+
+ char + report
long-offsets on
acpi-io-base 4 + port-rw \ Get APCI Status register
@@ -138,9 +145,15 @@
\ This must be done in both the power-up and resume-from-S3 cases,
\ since the registers in D17F7 lose state during S3.
- total-size 8f60 config-wb \ DRAM Bank 7 ending address - controls DMA upstream
- 0388 config-rb ax bx mov 8fe5 config-setup bx ax mov al dx out \ Copy Low Top from RO reg 88 to SB Low Top e5
+ 0385 config-rb ax bx mov 8fe5 config-setup bx ax mov al dx out \ Copy Low Top from reg 85 to SB Low Top e5
+ 0385 config-rb ax bx mov 8f60 config-setup bx ax mov al dx out \ Copy Low Top from reg 85 to SB Bank 7 end 60
+
+\ d# 17 7 devfunc
+\ e6 ff 07 mreg \ Enable Top, High, and Compatible SMM
+\ end-table
+
+
fload ${BP}/cpu/x86/pc/olpc/via/startgfxinit.fth
0 [if] \ Fire up C Forth
@@ -167,8 +180,34 @@
h# ffff.0000 # ax mov ax jmp
[then]
-\ fload ${BP}/cpu/x86/pc/ramtest.fth
+0 [if]
+long-offsets on
+acpi-io-base 48 + port-rl h# 1000.0000 # ax and 0<> if \ Memory ID1 bit
+ mmxcr
+ 39 3c4 port-wb ax ax xor 3c5 port-rb ax mmxdot
+ 68 3c4 port-wb ax ax xor 3c5 port-rb ax mmxdot
+ 6d 3c4 port-wb ax ax xor 3c5 port-rb ax mmxdot
+ 6e 3c4 port-wb ax ax xor 3c5 port-rb ax mmxdot
+ 6f 3c4 port-wb ax ax xor 3c5 port-rb ax mmxdot mmxcr
+
+ h# 08b0 # ax mov ax mmxdot mmxcr
+ h# 08b0 h# 10 mmxcfg-dump
+
+ h# 0200 # ax mov ax mmxdot mmxcr
+ h# 0200 h# 100 mmxcfg-dump
+
+ h# 0300 # ax mov ax mmxdot mmxcr
+ h# 0300 h# 100 mmxcfg-dump
+
+ h# 00100000 # ax mov ax mmxdot mmxcr
+ h# 00100000 to ramtest-start
+ ramtest-start h# 1a00.0000 + to ramtest-end
+ fload ${BP}/cpu/x86/pc/ramtest.fth
+then
+long-offsets off
+[then]
+
fload ${BP}/cpu/x86/pc/olpc/via/startmtrrinit.fth
fload ${BP}/cpu/x86/pc/olpc/via/ioinit.fth
Modified: cpu/x86/pc/olpc/via/startgfxinit.fth
===================================================================
--- cpu/x86/pc/olpc/via/startgfxinit.fth 2009-10-02 22:00:49 UTC (rev 1387)
+++ cpu/x86/pc/olpc/via/startgfxinit.fth 2009-10-02 22:03:37 UTC (rev 1388)
@@ -11,20 +11,21 @@
\ de ff 06 mreg \ Enable CHA and CHB merge mode (but description says this value disable merging!) 00 for compatibility
end-table
-\ 0 3 devfunc
-\ a1 70 40 mreg \ Set frame buffer size to 64M (8M:10, 16M:20, 32M:30, etc) - fbsize
-\ end-table
-
1 0 devfunc
- \ Reg 1b2 controls the number of writable bits in the BAR at 810
- b2 ff 70 mreg \ Offset of frame buffer, depends on size - fbsize
- 04 ff 07 mreg \ Enable IO and memory access to display
+ \ Reg 1b2 is a mask of the number of writable bits in the BAR at 810
+ \ It depends on the size that is chosen for the frame buffer memory
+ /fbmem 1- invert d# 22 rshift h# 7f also forth and previous
+ b2 ff rot mreg \ Offset of frame buffer, depends on size
+ 04 ff 07 mreg \ Enable IO and memory access to display
end-table
- d000.0000 810 config-wl \ S.L. Base address
- f000.0000 814 config-wl \ MMIO Base address
- cd01 3a0 config-ww \ Set frame buffer size and CPU-relative address and enable
+ fb-pci-base 810 config-wl \ S.L. Base address
+ gfx-pci-base 814 config-wl \ MMIO Base address
+ /fbmem log2 d# 22 - d# 12 lshift
+ fb-pci-base d# 21 rshift 1 lshift +
+ h# 8001 + 3a0 config-ww \ Set frame buffer size and CPU-relative address and enable
+
0 0 devfunc
c6 02 02 mreg \ Enable MDA forwarding (not in coreboot)
d4 00 03 mreg \ Enable MMIO and S.L. access in Host Control device
@@ -39,25 +40,35 @@
10 3c4 port-wb 01 3c5 port-wb \ Turn off register protection
67 3c2 port-wb \ Enable CPU Display Memory access (2), use color not mono port (1)
- 68 3c4 port-wb e0 3c5 port-wb \ Size of System Local Frame Buffer - Value depends on frame buffer size - fbsize
+ /fbmem 1- invert d# 21 rshift ( size-code )
+ 68 3c4 port-wb ( size ) 3c5 port-wb \ Size of System Local Frame Buffer - Value depends on frame buffer size
\ 00:512MB 80:256MB c0:128MB e0:64MB f0:32MB f8:16MB fc:8MB fe:4MB ff:2MB
\ These 2 are scratch registers that communicate with the VGA BIOS
3d 3d4 port-wb 74 3d5 port-wb \ Value depends on DIMM frequency - used by VGA BIOS
- 39 3c4 port-wb 10 3c5 port-wb \ BIOS Reserved Register 0 - FBsize_MiB/4 - fbsize - VGA BIOS
+ 39 3c4 port-wb /fbmem d# 22 rshift 3c5 port-wb \ BIOS Reserved Register 0 - FBsize_MiB/4 - VGA BIOS
5a 3c4 port-wb 01 3c5 port-wb \ Point to secondary registers
4c 3c4 port-wb 83 3c5 port-wb \ LCDCK Clock Synthesizer Value 2
5a 3c4 port-wb 00 3c5 port-wb \ Point back to primary registers
- 6d 3c4 port-wb e0 3c5 port-wb \ Base address [28:21] of SL in System Memory - base is 1c00.0000 - fbsize, memsize
+
[ifdef] demo-board
- 6e 3c4 port-wb 00 3c5 port-wb \ Base address [36:29] of SL in System Memory
+ 6d 3c4 port-wb total-size >fbmem-base drop 3c5 port-wb \ Base address [28:21] of SL in System Memory
+ 6e 3c4 port-wb total-size >fbmem-base nip 3c5 port-wb \ Base address [36:29] of SL in System Memory
+ 6f 3c4 port-wb 00 3c5 port-wb \ Base address [47:37] of SL in System Memory
[then]
[ifdef] xo-board
- 6e 3c4 port-wb 01 3c5 port-wb \ Base address [36:29] of SL in System Memory
+ 385 config-rb \ AX: totalsize/16M
+ d# 24 # ax shl \ AX: totalsize
+ /fbmem # ax sub \ AX: totalsize-fbmemsize = fbbase
+ d# 21 # ax shr \ AX: fbbase/2M
+ ax bx mov \ BX: fbbase/2M
+
+ 6d 3c4 port-wb bl al mov 3c5 # dx mov al dx out \ Base address [28:21] of SL in System Memory
+ 6e 3c4 port-wb bh al mov 3c5 # dx mov al dx out \ Base address [36:29] of SL in System Memory
+ 6f 3c4 port-wb d# 16 # bx shr bl al mov 3c5 # dx mov al dx out \ Base address [47:37] of SL in System Memory
[then]
- 6f 3c4 port-wb 00 3c5 port-wb \ Base address [47:37] of SL in System Memory
36 3c4 port-wb 11 3c5 port-wb \ Subsystem Vendor ID 1
35 3c4 port-wb 06 3c5 port-wb \ Subsystem Vendor ID 0
Modified: cpu/x86/pc/olpc/via/starthostctl.fth
===================================================================
--- cpu/x86/pc/olpc/via/starthostctl.fth 2009-10-02 22:00:49 UTC (rev 1387)
+++ cpu/x86/pc/olpc/via/starthostctl.fth 2009-10-02 22:03:37 UTC (rev 1388)
@@ -66,3 +66,17 @@
51 ff f8 mreg \ Last step - enable DRDY timing
[then]
end-table
+
+ acpi-io-base 48 + port-rl h# 1000.0000 # ax and 0<> if \ Memory ID1 bit
+ 0 2 devfunc
+ 55 02 02 mreg \ Host controller to DRAM read cycle control II - 1 means 2T slower
+
+ 60 ff ff mreg \ DRDY Timing Control 1 for Read Line
+ 61 ff ff mreg \ DRDY Timing Control 2 for Read Line
+ 63 ff ff mreg \ DRDY Timing Control 1 for Read QW
+ 64 ff ff mreg \ DRDY Timing Control 2 for Read QW
+ 66 ff ff mreg \ Burst DRDR Timing Control for Second cycle in burst
+
+ 90 03 00 mreg \ Host controller to DRAM read cycle control III - 00 means 2T faster
+ end-table
+ then
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