[openfirmware] r1466 - cpu/x86/pc/olpc/via

[svn at openfirmware.info]

Author: wmb
Date: 2009-11-09 21:43:26 +0000 (Mon, 09 Nov 2009)
New Revision: 1466

Added:
   cpu/x86/pc/olpc/via/startclkgen.fth
Modified:
   cpu/x86/pc/olpc/via/clkgen.fth
   cpu/x86/pc/olpc/via/ioinit.fth
   cpu/x86/pc/olpc/via/romreset.bth
Log:
OLPC trac 9481 - Move the "turn off unused clock generator outputs" code
into the early-startup assembly language code so it will work in S3 resume too.


Modified: cpu/x86/pc/olpc/via/clkgen.fth
===================================================================
--- cpu/x86/pc/olpc/via/clkgen.fth	2009-11-09 21:04:45 UTC (rev 1465)
+++ cpu/x86/pc/olpc/via/clkgen.fth	2009-11-09 21:43:26 UTC (rev 1466)
@@ -23,14 +23,11 @@
    smbus-release                    ( )
 ;
 
+\ We don't need to call disable-unused-clocks in stand-init because
+\ it is done in early-startup so it will affect resume-from-S3 too.
 : disable-unused-clocks  ( -- )   h# 02 5 clkgen-b!  ;
 : enable-unused-clocks   ( -- )   h# de 5 clkgen-b!  ;
 
-stand-init: Clock generator
-   disable-unused-clocks
-;
-
-
 \ LICENSE_BEGIN
 \ Copyright (c) 2009 FirmWorks
 \ 

Modified: cpu/x86/pc/olpc/via/ioinit.fth
===================================================================
--- cpu/x86/pc/olpc/via/ioinit.fth	2009-11-09 21:04:45 UTC (rev 1465)
+++ cpu/x86/pc/olpc/via/ioinit.fth	2009-11-09 21:43:26 UTC (rev 1466)
@@ -263,7 +263,7 @@
 [then]
 
    d# 17 0 devfunc  \ Bus control and power management
-   04 40 40 mreg  \ Check parity
+   04 43 43 mreg  \ Check parity, enable I/O and memory access
    40 44 44 mreg  \ Enable I/O Recovery time (40), Enable ports 4d0/4d1 for edge/level setting (04)
 [ifdef] xo-board
    41 40 40 mreg  \ Enable fff0.0000-fff7.ffff ROM on LPC bus
@@ -339,7 +339,7 @@
    8d 18 18 mreg  \ fast clock as throttle timer tick, hold SMI# low until event status cleared
 [then]
    
-   94 ff 68 mreg  \ be like Phx
+   94 ff 68 mreg  \ be like Phx - importantly, clear the 80 bit so the SMBus clock comes from the 14 MHz divider
    95 ff cd mreg  \ 0x0c enables GPIO0,1 (per datasheet; programmer's manual is vague)
 [ifdef] demo-board
    97 ff 80 mreg  \ be like Phx 
@@ -377,7 +377,7 @@
 smbus-io-base wbsplit swap  ( bits15:8 bits7:0 )
    d0 f0 rot mreg  \ SMBUS IO Base Address low (port is 0500)
    d1 ff rot mreg  \ SMBUS IO Base Address high
-   d2 0f 01 mreg  \ Enable SMBUS and set other characteristics
+   d2 0f 05 mreg  \ Enable SMBUS and set divider
 \  e2 80 80 mreg  \ Inhibit C4 during USB isochronous transaction
    e2 ff e9 mreg  \ Inhibit C4 during USB isochronous transaction, other bits reserved - Phoenix value
 [ifdef] demo-board

Modified: cpu/x86/pc/olpc/via/romreset.bth
===================================================================
--- cpu/x86/pc/olpc/via/romreset.bth	2009-11-09 21:04:45 UTC (rev 1465)
+++ cpu/x86/pc/olpc/via/romreset.bth	2009-11-09 21:43:26 UTC (rev 1466)
@@ -216,7 +216,7 @@
    fload ${BP}/cpu/x86/pc/olpc/via/startmtrrinit.fth
 
    fload ${BP}/cpu/x86/pc/olpc/via/ioinit.fth
-
+   fload ${BP}/cpu/x86/pc/olpc/via/startclkgen.fth    \ Turn off unused clock generator outputs
    fload ${BP}/cpu/x86/pc/olpc/via/starttherm.fth     \ Enables thermal monitor
    fload ${BP}/cpu/x86/pc/olpc/via/startcpuspeed.fth  \ Turns up clock rate
 

Added: cpu/x86/pc/olpc/via/startclkgen.fth
===================================================================
--- cpu/x86/pc/olpc/via/startclkgen.fth	                        (rev 0)
+++ cpu/x86/pc/olpc/via/startclkgen.fth	2009-11-09 21:43:26 UTC (rev 1466)
@@ -0,0 +1,16 @@
+\ We depend on ioinit.fth having already established the following settings 
+\ D17F0 Rx04[0]=1  I/O space enable
+\ D17F0 Rx94[7]=0  Clock from 14 MHz divider
+\ D17F0 Rxd2[2]=1  Clock divider
+\ D17F0 Rxd2[0]=1  Enable SMBus host controller
+\ D17F0 Rxd0,d1 set to smbus-io-base
+
+h# de smbus-io-base 0 + port-wb   \ Clear all errors
+\ We assume that the SMBus controller is not busy
+h# d2 smbus-io-base 4 + port-wb   \ Target address of clock generator chip and WRITE mode
+h# 05 smbus-io-base 3 + port-wb   \ Register number inside clock generator (output config)
+h# 01 smbus-io-base 5 + port-wb   \ Byte count
+      smbus-io-base 2 + port-rb   \ Read to reset the byte counter for the next write
+h# 02 smbus-io-base 7 + port-wb   \ Value to put in the clock generator output config reg - turns of PCIe clocks
+h# 54 smbus-io-base 2 + port-wb   \ Fire off the command.  40 is the start bit, 14 is the "SMBus block data" command
+\ We don't wait for it to finish